公开(公告)号：US20160372382A1

公开(公告)日：2016-12-22

申请号：US15158885

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HUYONG LEE ,  Wandon KIM ,  Jaeyeol SONG ,  Sangjin HYUN

IPC: H01L21/8238 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor device includes a gate structure crossing an active pattern of a substrate. The semiconductor device may include a gate dielectric pattern between the substrate and the gate electrode. The gate structure includes a gate electrode, a capping pattern on the gate electrode, and one or more low-k dielectric layers at least partially covering one or more sidewalls of the capping pattern. The gate structure may include spacers at opposite sidewalk of the gate electrode and separate low-k dielectric layers between the capping pattern and the spacers. The capping pattern may have a width that is smaller than a width of the gate electrode. The capping pattern has a first dielectric constant, and the one or more low-k dielectric layers have a second dielectric constant. The second dielectric constant is smaller than the first dielectric constant. The second dielectric constant may he greater than or equal to 1.

Abstract translation: 半导体器件包括与衬底的有源图案交叉的栅极结构。 半导体器件可以包括在衬底和栅电极之间的栅极电介质图案。 栅极结构包括栅电极，栅电极上的覆盖图案以及至少部分覆盖封盖图案的一个或多个侧壁的一个或多个低k电介质层。 栅极结构可以包括在栅电极的相对的人行道处的隔离物和封盖图案和间隔物之间​​的分离的低k电介质层。 封盖图案的宽度可以小于栅电极的宽度。 封盖图案具有第一介电常数，并且一个或多个低k电介质层具有第二介电常数。 第二介电常数小于第一介电常数。 第二介电常数可以大于或等于1。