公开(公告)号：US20230402523A1

公开(公告)日：2023-12-14

申请号：US18103897

申请日：2023-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeyeol SONG ,  Ohseong Kwon ,  Suyoung Bae ,  Sangyong Kim

IPC: H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/42392 ,  H01L29/775 ,  H01L29/0673 ,  H01L27/088

Abstract: A semiconductor device includes first and second active patterns respectively provided on a first and second PMOSFET regions of a substrate, a first channel pattern on the first active pattern, the first channel pattern including first semiconductor patterns stacked and spaced apart from each other, a second channel pattern on the second active pattern, the second channel pattern including second semiconductor patterns stacked and spaced apart from each other, a first gate electrode on the first channel pattern, and a second gate electrode on the second channel pattern. A first concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the first gate electrode is different from a second concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the second gate electrode.

公开(公告)号：US20170005175A1

公开(公告)日：2017-01-05

申请号：US15186982

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol SONG ,  Wandon KIM ,  Hoonjoo NA ,  Suyoung BAE ,  Hyeok-Jun SON ,  Sangjin HYUN

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/085

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may he between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有共同导电类型的多个有源区和在分离的有源区上分开的相应的栅电极。 不同的高k电介质层可以在分离的有源区和有源区上的相应栅电极之间。 不同数量的高k电介质层可以在分离的有源区域和有源区域上的相应栅电极之间。 不同的高k电介质层可以包括不同的功函调整材料。

公开(公告)号：US20230361121A1

公开(公告)日：2023-11-09

申请号：US18353214

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun CHUNG ,  Hoonjoo NA ,  Suyoung BAE ,  Jaeyeol SONG ,  Jonghan LEE ,  HyungSuk JUNG ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L29/78696 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/42392

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20210358910A1

公开(公告)日：2021-11-18

申请号：US17384920

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun CHUNG ,  Hoonjoo NA ,  Suyoung BAE ,  Jaeyeol SONG ,  Jonghan LEE ,  HyungSuk JUNG ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20180026112A1

公开(公告)日：2018-01-25

申请号：US15720812

申请日：2017-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonkyu PARK ,  Hoonjoo NA ,  Jaeyeol SONG ,  Sangjin HYUN

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate pattern on the second area. The first gate pattern includes a first gate insulating pattern on the first area, a first gate barrier pattern on the first gate insulating pattern, and a first work function metal pattern on the first gate barrier pattern. The second gate pattern includes a second gate insulating pattern on the second area, a second gate barrier pattern on the second gate insulating pattern, and a second work function metal pattern on the second gate barrier pattern. The first gate barrier pattern includes a metal material different than the second gate barrier pattern.

公开(公告)号：US20160372382A1

公开(公告)日：2016-12-22

申请号：US15158885

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HUYONG LEE ,  Wandon KIM ,  Jaeyeol SONG ,  Sangjin HYUN

IPC: H01L21/8238 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor device includes a gate structure crossing an active pattern of a substrate. The semiconductor device may include a gate dielectric pattern between the substrate and the gate electrode. The gate structure includes a gate electrode, a capping pattern on the gate electrode, and one or more low-k dielectric layers at least partially covering one or more sidewalls of the capping pattern. The gate structure may include spacers at opposite sidewalk of the gate electrode and separate low-k dielectric layers between the capping pattern and the spacers. The capping pattern may have a width that is smaller than a width of the gate electrode. The capping pattern has a first dielectric constant, and the one or more low-k dielectric layers have a second dielectric constant. The second dielectric constant is smaller than the first dielectric constant. The second dielectric constant may he greater than or equal to 1.

Abstract translation: 半导体器件包括与衬底的有源图案交叉的栅极结构。 半导体器件可以包括在衬底和栅电极之间的栅极电介质图案。 栅极结构包括栅电极，栅电极上的覆盖图案以及至少部分覆盖封盖图案的一个或多个侧壁的一个或多个低k电介质层。 栅极结构可以包括在栅电极的相对的人行道处的隔离物和封盖图案和间隔物之间​​的分离的低k电介质层。 封盖图案的宽度可以小于栅电极的宽度。 封盖图案具有第一介电常数，并且一个或多个低k电介质层具有第二介电常数。 第二介电常数小于第一介电常数。 第二介电常数可以大于或等于1。