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    RESISTIVE MEMORY DEVICE CONTROLLING BITLINE VOLTAGE
    1.
    发明申请
    RESISTIVE MEMORY DEVICE CONTROLLING BITLINE VOLTAGE 有权

    公开(公告)号：US20210151101A1

    公开(公告)日：2021-05-20

    申请号：US17036004

    申请日：2020-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  CHEONAN LEE ,  SATORU YAMADA ,  JUNHEE LIM

    IPC: G11C13/00 ,  H01L27/24

    Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.

    MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME
    2.
    发明申请
    MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20210193661A1

    公开(公告)日：2021-06-24

    申请号：US17032040

    申请日：2020-09-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  SATORU YAMADA ,  SUNGWON YOO ,  JAEHO HONG

    IPC: H01L27/108 ,  G11C7/18

    Abstract: Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

    SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS
    3.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS 审中-公开
    包括晶体管的半导体器件

    公开(公告)号：US20160163708A1

    公开(公告)日：2016-06-09

    申请号：US14957169

    申请日：2015-12-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNG-HO JANG ,  SATORU YAMADA ,  JUN-HEE LIM ,  JU-YEON JANG ,  KYOUNG-HO JUNG ,  JOON HAN

    IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4091 ,  H01L27/02 ,  H01L27/092

    CPC classification number: G11C11/4087 ,  G11C11/4085 ,  G11C11/4091 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/10894 ,  H01L27/10897

    Abstract: A semiconductor device includes a semiconductor substrate having a first transistor region and a second transistor region, a first MOSFET including a first gate insulating layer structure and a first gate electrode structure, and a second MOSFET including a group IV compound semiconductor layer, a second gate insulating layer structure, and a second gate electrode structure. The first gate insulating layer structure and the first gate electrode structure are disposed on the first transistor region of the semiconductor substrate. The group IV compound semiconductor layer is disposed on the second transistor region of the semiconductor substrate, and the second gate insulating layer and the second gate electrode structure are disposed on the group IV compound semiconductor layer. Each of the first and second gate insulating layer structures includes a high-k dielectric (insulating) layer.

    Abstract translation: 半导体器件包括具有第一晶体管区域和第二晶体管区域的半导体衬底，包括第一栅极绝缘层结构和第一栅极电极结构的第一MOSFET以及包括IV族化合物半导体层的第二MOSFET，第二栅极 绝缘层结构和第二栅电极结构。 第一栅极绝缘层结构和第一栅电极结构设置在半导体衬底的第一晶体管区域上。 IV族化合物半导体层设置在半导体衬底的第二晶体管区域上，第二栅极绝缘层和第二栅电极结构设置在IV族化合物半导体层上。 第一和第二栅极绝缘层结构中的每一个包括高k电介质（绝缘）层。

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