Operating method of host device and storage device using credit

    公开(公告)号:US11593031B2

    公开(公告)日:2023-02-28

    申请号:US17375328

    申请日:2021-07-14

    Abstract: An electronic device may include a host device and a storage device which are connected in a universal flash storage standard, wherein the host device may include processing circuitry configured to process a submission queue (SQ) and a completion queue (CQ), wherein the SQ is a processing standby line of a command, and the CQ is a processing standby line of a response received from the storage device, transmit the command to the storage device, store a host command credit in a host command register, the host command credit indicating an estimated command accommodation limit of the storage device, store the response in a response slot, and store a host response credit in a host command register, the host command credit indicating a limit of the response slot.

    Image sensor and semiconductor device including asymmetric active region

    公开(公告)号:US12191332B2

    公开(公告)日:2025-01-07

    申请号:US17526424

    申请日:2021-11-15

    Abstract: An image sensor includes: a first device isolation part in a substrate and defining an active region; a first gate electrode having a first and second gate sidewalls; and a first impurity region and a second impurity region adjacent to the first and second gate sidewalls, wherein the active region includes: a first active central part; a first active protrusion; and a second active protrusion, wherein the first device isolation part has a first isolation sidewall overlapping the first active central part, and wherein a first straight line is at least partially spaced apart from the first isolation sidewall, wherein the first straight line links a first point, at which the first active protrusion meets the first active central part, to a second point, at which the second active protrusion meets the first active central part.

    Host controller interface using multiple circular queue, and operating method thereof

    公开(公告)号:US11561912B2

    公开(公告)日:2023-01-24

    申请号:US17321916

    申请日:2021-05-17

    Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.

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