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1.发明申请公开(公告)号：US20210334225A1
公开(公告)日：2021-10-28
申请号：US17241564
申请日：2021-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungho Seo , Kwanwoo Noh , Myungsub Shin , Dongwoo Nam
Abstract: A storage device capable of performing high-speed link startup and a storage system including the storage device are disclosed. A link startup method of the storage device includes receiving a line-reset signal from a host through a line connected to an input signal pin of the storage device, comparing a length of the received line-reset signal with a first reference time, and performing a link startup operation in a high-speed mode or a low-speed mode between the storage device and the host according to a comparing result.
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公开(公告)号：US11934691B2
公开(公告)日：2024-03-19
申请号：US18304782
申请日：2023-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongwoo Nam , Sungho Seo , Kwanwoo Noh , Myungsub Shin , Haesung Jung
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F13/1668 , G06F13/385 , G06F13/4278
Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.
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Patent Agency Ranking
公开(公告)号：US11675531B2
公开(公告)日：2023-06-13
申请号：US17328225
申请日：2021-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongwoo Nam , Sungho Seo , Kwanwoo Noh , Myungsub Shin , Haesung Jung
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F13/1668 , G06F13/385 , G06F13/4278
Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.
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4.发明授权公开(公告)号：US11625342B2
公开(公告)日：2023-04-11
申请号：US17241564
申请日：2021-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungho Seo , Kwanwoo Noh , Myungsub Shin , Dongwoo Nam
Abstract: A storage device capable of performing high-speed link startup and a storage system including the storage device are disclosed. A link startup method of the storage device includes receiving a line-reset signal from a host through a line connected to an input signal pin of the storage device, comparing a length of the received line-reset signal with a first reference time, and performing a link startup operation in a high-speed mode or a low-speed mode between the storage device and the host according to a comparing result.
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公开(公告)号：US12130655B2
公开(公告)日：2024-10-29
申请号：US18508479
申请日：2023-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo Noh , Sungho Seo , Yongwoo Jeong , Dongwoo Nam , Myungsub Shin , Hyunkyu Jang
CPC classification number: G06F1/08 , G06F1/04 , G06F3/0632 , G06F3/0658 , G06F3/0679 , G06F13/4291 , G11C7/22 , G11C16/32 , H04L7/0004 , H04L7/0008
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
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公开(公告)号：US11874695B2
公开(公告)日：2024-01-16
申请号：US18064002
申请日：2022-12-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo Noh , Sungho Seo , Yongwoo Jeong , Dongwoo Nam , Myungsub Shin , Hyunkyu Jang
CPC classification number: G06F1/08 , G06F1/04 , G06F3/0632 , G06F3/0658 , G06F3/0679 , G06F13/4291 , G11C7/22 , G11C16/32 , H04L7/0004 , H04L7/0008
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
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公开(公告)号：US11561571B2
公开(公告)日：2023-01-24
申请号：US17179830
申请日：2021-02-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo Noh , Sungho Seo , Yongwoo Jeong , Dongwoo Nam , Myungsub Shin , Hyunkyu Jang
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
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