公开(公告)号：US20170053806A1

公开(公告)日：2017-02-23

申请号：US15239364

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunglyong KANG ,  Youngmok KIM ,  Hodae OH ,  Kyoung-Eun UHM

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A method for manufacturing a semiconductor device includes forming a device isolation layer in a substrate to define an active region, forming a gate insulating layer covering at least a portion of the active region, forming a gate electrode on the gate insulating layer, and forming an interlayer insulating layer on the gate electrode. The gate insulating layer includes a first portion overlapping with the active region and a second portion overlapping with the device isolation layer. The forming of the gate insulating layer includes etching at least a part of the second portion of the gate insulating layer to thin the part of the second portion of the gate insulating layer.

Abstract translation: 一种制造半导体器件的方法包括在衬底中形成器件隔离层以限定有源区，形成覆盖有源区的至少一部分的栅极绝缘层，在栅极绝缘层上形成栅电极， 栅电极上的层间绝缘层。 栅极绝缘层包括与有源区重叠的第一部分和与器件隔离层重叠的第二部分。 栅极绝缘层的形成包括蚀刻栅极绝缘层的第二部分的至少一部分，以使栅极绝缘层的第二部分的一部分变薄。