公开(公告)号：US11848068B2

公开(公告)日：2023-12-19

申请号：US17851255

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungsul Kim ,  Hokyong Lee ,  Hwajin Jung ,  Yongjoo Choi

IPC: G11C29/44 ,  G11C29/34 ,  G11C29/14 ,  G11C7/10 ,  G11C29/12 ,  G11C29/18

CPC classification number: G11C29/44 ,  G11C7/1045 ,  G11C29/14 ,  G11C29/34 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.

公开(公告)号：US20220328122A1

公开(公告)日：2022-10-13

申请号：US17851255

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungsul KIM ,  Hokyong Lee ,  Hwajin Jung ,  Yongjoo Choi

IPC: G11C29/44 ,  G11C29/34 ,  G11C29/14 ,  G11C7/10

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.

公开(公告)号：US11664083B2

公开(公告)日：2023-05-30

申请号：US16855373

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungsul Kim ,  Hokyong Lee ,  Dongjun Kim ,  Byungmin Choi ,  Kideok Han

IPC: G11C29/14 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C29/42 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/14 ,  G11C29/44 ,  G11C29/78 ,  G11C2029/4402

Abstract: A memory system including a first central processing unit, a first memory module connected to the first central processing unit by a first channel, a second memory module connected to the first central processing unit by a second channel, and a third memory module connected to the first central processing unit by a third channel may be provided. Each of the first memory module, the second memory module, and the third memory module may be configured to write the same data in a data area thereof and a mirroring data area thereof in response to an address in a mirroring mode.