公开(公告)号：US11664083B2

公开(公告)日：2023-05-30

申请号：US16855373

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungsul Kim ,  Hokyong Lee ,  Dongjun Kim ,  Byungmin Choi ,  Kideok Han

IPC: G11C29/14 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C29/42 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/14 ,  G11C29/44 ,  G11C29/78 ,  G11C2029/4402

Abstract: A memory system including a first central processing unit, a first memory module connected to the first central processing unit by a first channel, a second memory module connected to the first central processing unit by a second channel, and a third memory module connected to the first central processing unit by a third channel may be provided. Each of the first memory module, the second memory module, and the third memory module may be configured to write the same data in a data area thereof and a mirroring data area thereof in response to an address in a mirroring mode.

公开(公告)号：US11797450B2

公开(公告)日：2023-10-24

申请号：US17232844

申请日：2021-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungsul Kim ,  Youngsan Kang ,  Daehyun Kwon ,  Myong-Seob Song ,  Byung Yo Lee ,  Yejin Jo

IPC: G06F12/0815 ,  G06F12/0804

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F2212/1032

Abstract: An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.

公开(公告)号：US12073865B2

公开(公告)日：2024-08-27

申请号：US17851794

申请日：2022-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Shim ,  Byoungsul Kim ,  Joonmin Park ,  Sungtack Hong

IPC: G06F1/26 ,  G06F1/3225 ,  G11C11/406 ,  G11C11/4096 ,  G06F1/3203 ,  H02M1/44

CPC classification number: G11C11/406 ,  G06F1/3225 ,  G11C11/4096 ,  G06F1/3203 ,  H02M1/44

Abstract: Disclosed is a user system which includes a first device and a second device, which share a shared voltage, and a power management integrated circuit (PMIC) generating the shared voltage. An operation method of the user system includes performing a first operation of the first device, determining whether a second operation of the second device is to be performed while the first device performs the first operation, based on an operation profile, and when it is determined that the second operation of the second device is to be performed while the first device performs the first operation, changing a power mode of the PMIC from a first power mode to a second power mode, before the second device performs the second operation. The PMIC generates the shared voltage based on the first power mode or the second power mode.

公开(公告)号：US11848068B2

公开(公告)日：2023-12-19

申请号：US17851255

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungsul Kim ,  Hokyong Lee ,  Hwajin Jung ,  Yongjoo Choi

IPC: G11C29/44 ,  G11C29/34 ,  G11C29/14 ,  G11C7/10 ,  G11C29/12 ,  G11C29/18

CPC classification number: G11C29/44 ,  G11C7/1045 ,  G11C29/14 ,  G11C29/34 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.