公开(公告)号：US09978865B2

公开(公告)日：2018-05-22

申请号：US15385060

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hong Kwon ,  Youngho Lee ,  Hoon Lim ,  Hyungsoon Jang ,  Eunguk Chung

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L27/11 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/0852 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

公开(公告)号：US20180219094A1

公开(公告)日：2018-08-02

申请号：US15928516

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hong Kwon ,  Youngho Lee ,  Hoon Lim ,  Hyungsoon Jang ,  Eunguk Chung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/08 ,  H01L27/092 ,  H01L27/11

CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/0852 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

公开(公告)号：US20150061039A1

公开(公告)日：2015-03-05

申请号：US14535851

申请日：2014-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Lim

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.

Abstract translation: 提供半导体器件及其制造方法。 根据半导体器件，在器件隔离层上的栅极图案的两个侧壁的至少一部分上形成硅化物层，从而降低栅极图案的电阻。 这使得设备的操作速度快。 根据半导体器件的方法，在随后的自对准硅化物工艺中，在栅极图案的两个侧壁的至少一部分上形成侧壁间隔图案，通过完全或部分地去除侧壁间隔物的剩余部分，除了用作 离子注入掩模以形成源极/漏极区域。 这可以降低栅极图案的电阻，从而制造具有快速操作速度的半导体器件。

公开(公告)号：US20130341732A1

公开(公告)日：2013-12-26

申请号：US14013853

申请日：2013-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Lim

IPC: H01L27/088

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.

公开(公告)号：US10269958B2

公开(公告)日：2019-04-23

申请号：US15928516

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hong Kwon ,  Youngho Lee ,  Hoon Lim ,  Hyungsoon Jang ,  Eunguk Chung

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L21/8238 ,  H01L49/02 ,  H01L29/10 ,  H01L29/165

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

公开(公告)号：US09281377B2

公开(公告)日：2016-03-08

申请号：US14535851

申请日：2014-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Lim

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.

Abstract translation: 提供半导体器件及其制造方法。 根据半导体器件，在器件隔离层上的栅极图案的两个侧壁的至少一部分上形成硅化物层，从而降低栅极图案的电阻。 这使得设备的操作速度快。 根据半导体器件的方法，在随后的自对准硅化物工艺中，在栅极图案的两个侧壁的至少一部分上形成侧壁间隔图案，通过完全或部分地去除侧壁间隔物的剩余部分，除了用作 离子注入掩模以形成源极/漏极区域。 这可以降低栅极图案的电阻，从而制造具有快速操作速度的半导体器件。

公开(公告)号：US08916941B2

公开(公告)日：2014-12-23

申请号：US14013853

申请日：2013-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Lim

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed.

Abstract translation: 提供半导体器件及其制造方法。 根据半导体器件，在器件隔离层上的栅极图案的两个侧壁的至少一部分上形成硅化物层，从而降低栅极图案的电阻。 这使得设备的操作速度快。 根据半导体器件的方法，在随后的自对准硅化物工艺中，在栅极图案的两个侧壁的至少一部分上形成侧壁间隔图案，通过完全或部分地去除侧壁间隔物的剩余部分，除了用作 离子注入掩模以形成源极/漏极区域。 这可以降低栅极图案的电阻，从而制造具有快速操作速度的半导体器件。