公开(公告)号：US09978865B2

公开(公告)日：2018-05-22

申请号：US15385060

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hong Kwon ,  Youngho Lee ,  Hoon Lim ,  Hyungsoon Jang ,  Eunguk Chung

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L27/11 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/0852 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

公开(公告)号：US20180219094A1

公开(公告)日：2018-08-02

申请号：US15928516

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hong Kwon ,  Youngho Lee ,  Hoon Lim ,  Hyungsoon Jang ,  Eunguk Chung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/08 ,  H01L27/092 ,  H01L27/11

CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/0852 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

公开(公告)号：US10269958B2

公开(公告)日：2019-04-23

申请号：US15928516

申请日：2018-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hong Kwon ,  Youngho Lee ,  Hoon Lim ,  Hyungsoon Jang ,  Eunguk Chung

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/11 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L21/8238 ,  H01L49/02 ,  H01L29/10 ,  H01L29/165

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

公开(公告)号：US09576613B2

公开(公告)日：2017-02-21

申请号：US14571634

申请日：2014-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Steve Sunhom Paak ,  Kangwook Park ,  Heonjong Shin ,  Sunil Yu ,  Jongmil Youn ,  Hyungsoon Jang

IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  G11C29/12 ,  G11C29/48 ,  G11C29/56

CPC classification number: G11C5/06 ,  G11C5/02 ,  G11C5/025 ,  G11C8/14 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/5602

Abstract: A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors.

Abstract translation: 半导体器件可以包括半导体衬底; 测试电路阵列区域; 半导体衬底上的焊盘区域和测试电路阵列区域的至少第一侧以及测试电路阵列区域的外部，在第一方向和垂直于第一方向的第二方向上布置在测试电路阵列区域中的晶体管 在第二方向上彼此间隔开的源极线，每个源极线在第一方向上延伸并且电连接到晶体管的相应源电极，以及在第二方向彼此间隔开的漏极线， 漏极线在第一方向上延伸并电连接到晶体管的漏电极。