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公开(公告)号：US11080218B2
公开(公告)日：2021-08-03
申请号：US16425105
申请日：2019-05-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Manjae Yang , Jangwoo Lee , Hwasuk Cho , Jeongdon Ihm
Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.
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公开(公告)号：US09418333B2
公开(公告)日：2016-08-16
申请号：US14165392
申请日：2014-01-27
Inventor： Jun Seok Kim , Jae Yoon Sim , Hyun Surk Ryu , Hwasuk Cho
IPC: G06F15/18 , G06N3/08 , G06N3/063 , G06N3/04 , G11C11/412
CPC classification number: G06N3/063 , G06N3/049 , G11C11/412
Abstract: A synapse array based on a static random access memory (SRAM), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits. At least one synapse circuit among the plurality of synapse circuits includes at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor.
Abstract translation: 提供了基于静态随机存取存储器（SRAM），脉冲整形器电路和神经形态系统的突触阵列。 突触阵列包括多个突触电路。 所述多个突触电路中的至少一个突触电路包括至少一个偏置晶体管和至少两个截止晶体管，并且所述至少一个突触电路被配置为对与所述至少一个连接的神经元电路的膜节点进行充电 使用通过所述至少一个偏置晶体管的子阈值漏电流的突触电路。
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公开(公告)号：US20250138940A1
公开(公告)日：2025-05-01
申请号：US18639856
申请日：2024-04-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hwasuk Cho , Seungwoo Yu , Byungkwan Chun
IPC: G06F11/10
Abstract: A nonvolatile memory device includes a plurality of latch groups, an address controller, an encoder, and a buffer. The address controller controls an input address and an output address to indicate one of the plurality of latch groups. The encoder receives sector data from a latch group corresponding to the output address among the plurality of latch groups and also compresses the received sector data. The buffer stores the compressed sector data. Among the plurality of latch groups, the compressed sector data stored in the buffer is overwritten in a latch group corresponding to the input address.
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4.发明申请公开(公告)号：US20200167298A1
公开(公告)日：2020-05-28
申请号：US16425105
申请日：2019-05-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Manjae Yang , Jangwoo Lee , Hwasuk Cho , Jeongdon Ihm
Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.
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