公开(公告)号：US20200167298A1

公开(公告)日：2020-05-28

申请号：US16425105

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manjae Yang ,  Jangwoo Lee ,  Hwasuk Cho ,  Jeongdon Ihm

IPC: G06F13/16 ,  G06F3/06 ,  G11C7/10

Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.

公开(公告)号：US11080218B2

公开(公告)日：2021-08-03

申请号：US16425105

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manjae Yang ,  Jangwoo Lee ,  Hwasuk Cho ,  Jeongdon Ihm

IPC: G06F13/16 ,  G11C7/10 ,  G06F3/06 ,  G11C8/12 ,  G11C5/04 ,  G11C8/06 ,  G11C16/06 ,  G11C16/08

Abstract: An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.

公开(公告)号：US12073917B2

公开(公告)日：2024-08-27

申请号：US17404510

申请日：2021-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Manjae Yang ,  Chiweon Yoon ,  Junha Lee ,  Byunghoon Jeong

IPC: G06F1/04 ,  G06F3/06 ,  G11C7/22 ,  G11C29/02 ,  G11C5/14

CPC classification number: G11C7/222 ,  G06F1/04 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C29/023 ,  G11C29/028 ,  G11C5/145

Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.

公开(公告)号：US11315651B1

公开(公告)日：2022-04-26

申请号：US17355825

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongkil Jung ,  Dongjin Shin ,  Manjae Yang ,  Byungsun Lee ,  Dongsu Jang

IPC: G11C27/00 ,  G11C5/14 ,  G11C7/10

Abstract: A non-volatile memory device includes a first and a second memory regions including first and second memory cells and first and second analog circuits, respectively; a control logic circuit determining on/off states of the analog circuits, and converting an external power supply voltage into an internal operating voltage for operation of each of the memory cells; and input/output circuit selecting an input/output memory region for performing input/output of data using the internal operating voltage, wherein input/output of data for the first and second memory cells are sequentially performed, and at least one of the each of the first and second analog circuits are turned on together while the input/output of data for the first memory cells is performed.