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公开(公告)号：US10904466B2
公开(公告)日：2021-01-26
申请号：US16038806
申请日：2018-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeok-Jong Lee
Abstract: A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code.
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2.发明授权公开(公告)号：US09681082B2
公开(公告)日：2017-06-13
申请号：US14521821
申请日：2014-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeok-Jong Lee
CPC classification number: H04N5/378 , H03M1/123 , H03M1/56 , H04N5/3745 , H04N5/3765
Abstract: Provided is an image sensor including a pixel array including a plurality of pixels and an analog-to-digital converter (ADC) configured to compare a reference voltage with an analog voltage output by the pixel array and latch and decode a comparison result. The ADC is controlled in response to clock information and a counter clock, which are obtained by expanding and encoding a master clock.
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公开(公告)号：US20140375858A1
公开(公告)日：2014-12-25
申请号：US14230365
申请日：2014-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeok-Jong Lee
IPC: H03K4/02 , H04N5/3745 , H04N5/378
CPC classification number: H03K4/026 , H04N5/37455 , H04N5/378
Abstract: A ramp signal generator includes a rising-edge current unit, a falling-edge current unit and a current-voltage converter. The rising-edge current unit provides a rising-edge output current that sequentially increases or decreases in synchronization with rising edges of a clock signal. The falling-edge current unit provides a falling-edge output current that sequentially increases or decreases in synchronization with falling edges of the clock signal. The current-voltage converter outputs a ramp voltage by converting a summed current of the rising-edge output current and the falling-edge output current.
Abstract translation: 斜坡信号发生器包括上升沿电流单元，下降沿电流单元和电流 - 电压转换器。 上升沿电流单元提供与时钟信号的上升沿同步地顺序增加或减少的上升沿输出电流。 下降沿电流单元提供与时钟信号的下降沿同步地顺序增加或减少的下降沿输出电流。 电流 - 电压转换器通过转换上升沿输出电流和下降沿输出电流的总和电流来输出斜坡电压。
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公开(公告)号：US10455227B2
公开(公告)日：2019-10-22
申请号：US15834296
申请日：2017-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yun-Hong Kim , Hyeok-Jong Lee , Hee-Sung Chae
IPC: H04N17/00 , H04N5/3745 , H04N5/357 , H04N5/343 , H04N5/378
Abstract: An image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter having a first counter for converting an analog signal into a digital signal, and an output buffer having a first memory. A first counter test result value generated as a test result for the first counter is stored in the first memory in a test mode. The output buffer outputs the first counter test result value from the first memory to an outside of the output buffer in response to a first selection signal. The output buffer further includes a reset logic circuit for resetting the first memory depending on whether the first counter test result value is output or not. The plurality of pixels generate the analog signal in response to incident light.
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公开(公告)号：US20180324416A1
公开(公告)日：2018-11-08
申请号：US15834296
申请日：2017-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yun-Hong Kim , Hyeok-Jong Lee , Hee-Sung Chae
IPC: H04N17/00 , H04N5/3745 , H04N5/378 , H04N5/343 , H04N5/357
CPC classification number: H04N17/002 , H04N5/343 , H04N5/3575 , H04N5/37455 , H04N5/378
Abstract: An image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter having a first counter for converting an analog signal into a digital signal, and an output buffer having a first memory. A first counter test result value generated as a test result for the first counter is stored in the first memory in a test mode. The output buffer outputs the first counter test result value from the first memory to an outside of the output buffer in response to a first selection signal. The output buffer further includes a reset logic circuit for resetting the first memory depending on whether the first counter test result value is output or not. The plurality of pixels generate the analog signal in response to incident light.
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Patent Agency Ranking
公开(公告)号：US09325301B2
公开(公告)日：2016-04-26
申请号：US14230365
申请日：2014-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeok-Jong Lee
IPC: G06G7/22 , H03K4/02 , H04N5/378 , H04N5/3745
CPC classification number: H03K4/026 , H04N5/37455 , H04N5/378
Abstract: A ramp signal generator includes a rising-edge current unit, a falling-edge current unit and a current-voltage converter. The rising-edge current unit provides a rising-edge output current that sequentially increases or decreases in synchronization with rising edges of a clock signal. The falling-edge current unit provides a falling-edge output current that sequentially increases or decreases in synchronization with falling edges of the clock signal. The current-voltage converter outputs a ramp voltage by converting a summed current of the rising-edge output current and the falling-edge output current.
Abstract translation: 斜坡信号发生器包括上升沿电流单元，下降沿电流单元和电流 - 电压转换器。 上升沿电流单元提供与时钟信号的上升沿同步地顺序增加或减少的上升沿输出电流。 下降沿电流单元提供与时钟信号的下降沿同步地顺序增加或减少的下降沿输出电流。 电流 - 电压转换器通过转换上升沿输出电流和下降沿输出电流的总和电流来输出斜坡电压。
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公开(公告)号：US20190098234A1
公开(公告)日：2019-03-28
申请号：US16038806
申请日：2018-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeok-Jong Lee
Abstract: A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code.
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8.发明授权Digital correlated double sampling circuit and image sensor including the same 有权数字相关双采样电路和图像传感器包括相同公开(公告)号：US09380246B2
公开(公告)日：2016-06-28
申请号：US14335304
申请日：2014-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeok-Jong Lee
IPC: H04N5/378
CPC classification number: H04N5/378
Abstract: A digital correlated double sampling (CDS) circuit includes a first latch unit, a second latch unit and a calculating unit. The first latch unit stores digital reset component data and digital image component data by latching a count signal in response to a first control signal. The second latch unit stores the digital reset component data by latching an output of the first latch unit in response to a second control signal. The calculating unit generates digital effective image data by subtracting the digital reset component data from the digital image component data.
Abstract translation: 数字相关双采样（CDS）电路包括第一锁存单元，第二锁存单元和计算单元。 第一锁存单元通过响应于第一控制信号锁存计数信号来存储数字复位分量数据和数字图像分量数据。 第二锁存单元响应于第二控制信号锁存第一锁存单元的输出来存储数字复位分量数据。 计算单元通过从数字图像分量数据中减去数字复位分量数据来生成数字有效图像数据。
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9.发明申请Digital Correlated Double Sampling Circuit and Image Sensor Including the Same 有权数字相关双采样电路和包括其的图像传感器公开(公告)号：US20150138408A1
公开(公告)日：2015-05-21
申请号：US14335304
申请日：2014-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeok-Jong Lee
CPC classification number: H04N5/378
Abstract: A digital correlated double sampling (CDS) circuit includes a first latch unit, a second latch unit and a calculating unit. The first latch unit stores digital reset component data and digital image component data by latching a count signal in response to a first control signal. The second latch unit stores the digital reset component data by latching an output of the first latch unit in response to a second control signal. The calculating unit generates digital effective image data by subtracting the digital reset component data from the digital image component data.
Abstract translation: 数字相关双采样（CDS）电路包括第一锁存单元，第二锁存单元和计算单元。 第一锁存单元通过响应于第一控制信号锁存计数信号来存储数字复位分量数据和数字图像分量数据。 第二锁存单元响应于第二控制信号锁存第一锁存单元的输出来存储数字复位分量数据。 计算单元通过从数字图像分量数据中减去数字复位分量数据来生成数字有效图像数据。
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公开(公告)号：US11310488B2
公开(公告)日：2022-04-19
申请号：US17018120
申请日：2020-09-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyeok-Jong Lee
Abstract: In a method of operating an image sensor, the image sensor includes a pixel array and a plurality of column driving circuits that are connected to a plurality of columns of the pixel array. A test operation is performed by applying a test pattern to the plurality of column driving circuits while changing a level of a well-bias voltage applied to a transistor included in the plurality of column driving circuits. A bias setting operation for setting the level of the well-bias voltage is performed based on a result of the test operation. An image capture operation for detecting incident light and generating a frame image is performed based on the pixel array, the plurality of column driving circuits and the well-bias voltage set by the bias setting operation.
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