公开(公告)号：US10332831B2

公开(公告)日：2019-06-25

申请号：US15638552

申请日：2017-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Augustin Jinwoo Hong ,  Dae-Ik Kim ,  Chan-Sic Yoon ,  Ki-Seok Lee ,  Dong-Min Han ,  Sung-Ho Jang ,  Yoo-Sang Hwang ,  Bong-Soo Kim ,  Je-Min Park

IPC: H01L27/108 ,  H01L23/522 ,  H01L27/11568 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

公开(公告)号：US11574912B2

公开(公告)日：2023-02-07

申请号：US17112195

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo Hong ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US10886277B2

公开(公告)日：2021-01-05

申请号：US16106087

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo Hong ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US10141316B2

公开(公告)日：2018-11-27

申请号：US15275827

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Seok Lee ,  Jeong Seop Shim ,  Mi Na Lee ,  Augustin Jinwoo Hong ,  Je Min Park ,  Hye Jin Seong ,  Seung Min Oh ,  Do Yeong Lee ,  Ji Seung Lee ,  Jin Seong Lee

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.

公开(公告)号：US10522550B2

公开(公告)日：2019-12-31

申请号：US16183826

申请日：2018-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok Lee ,  Jeong Seop Shim ,  Mi Na Lee ,  Augustin Jinwoo Hong ,  Je Min Park ,  Hye Jin Seong ,  Seung Min Oh ,  Do Yeong Lee ,  Ji Seung Lee ,  Jin Seong Lee

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.

公开(公告)号：US09899487B2

公开(公告)日：2018-02-20

申请号：US15404703

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Hye-Young Kang ,  Young-Sin Kim ,  Yong-Kwan Kim ,  Byoung-Wook Jang ,  Augustin Jinwoo Hong ,  Dong-Sik Kong ,  Chang-Hyun Cho

IPC: H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L29/94 ,  H01L21/336 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.

公开(公告)号：US20170263723A1

公开(公告)日：2017-09-14

申请号：US15404703

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  Hye-Young Kang ,  Young-Sin Kim ,  Yong-Kwan Kim ,  Byoung-Wook Jang ,  Augustin Jinwoo Hong ,  Dong-Sik Kong ,  Chang-Hyun Cho

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.