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公开(公告)号：US20230093076A1
公开(公告)日：2023-03-23
申请号：US17677654
申请日：2022-02-22
发明人： Hagyoul BAE , Seunggeol NAM , Jinseong HEO , Sanghyun JO , Dukhyun CHOE
摘要： Provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. A ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 1016 cm−3eV−1 or more and an interface defect density of 1010 cm−2eV−1 or more.
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2.发明公开公开(公告)号：US20230275150A1
公开(公告)日：2023-08-31
申请号：US18168699
申请日：2023-02-14
发明人： Hyunjae LEE , Jinseong HEO , Seunggeol NAM , Taehwan MOON , Hagyoul BAE
CPC分类号： H01L29/78391 , H01L29/7606
摘要： A semiconductor device may include a semiconductor substrate including a dopant having a polarity; a channel layer on the semiconductor substrate and including majority carriers having a polarity opposite to a polarity of the semiconductor substrate; a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. A doping concentration of the semiconductor substrate may be less than a concentration of the majority carrier of the channel layer.
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公开(公告)号：US20220173099A1
公开(公告)日：2022-06-02
申请号：US17491841
申请日：2021-10-01
发明人： Sangwook KIM , Seunggeol NAM , Taehwan MOON , Kwanghee LEE , Jinseong HEO , Hagyoul BAE , Yunseong LEE
IPC分类号： H01L27/092 , H01L27/11 , H01L29/24 , H01L29/51 , H01L29/78 , H01L29/786
摘要： Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.
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公开(公告)号：US20220140148A1
公开(公告)日：2022-05-05
申请号：US17515984
申请日：2021-11-01
发明人： Seunggeol NAM , Jinseong HEO , Sangwook KIM , Hagyoul BAE , Taehwan MOON , Yunseong LEE
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/51
摘要： Provided is a ferroelectric semiconductor device including a source and a drain having different polarities. The ferroelectric semiconductor may include a ferroelectric including zirconium oxide (ZrO2), hafnium oxide (HfO2), and/or hafnium-zirconium oxide (HfxZr1−xO, 0
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公开(公告)号：US20230099577A1
公开(公告)日：2023-03-30
申请号：US17953491
申请日：2022-09-27
发明人： Jinseong HEO , Hagyoul BAE , Seunggeol NAM , Hyunjae LEE , Dukhyun CHOE
IPC分类号： G11C15/04
摘要： Provided is a content-addressable memory. The content-addressable memory may include a memory cell connected to a match line, a word line, and a search line, and the memory cell includes a first channel layer and a second channel layer doped with different dopants.
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公开(公告)号：US20230062878A1
公开(公告)日：2023-03-02
申请号：US17894504
申请日：2022-08-24
发明人： Jinseong HEO , Yunseong LEE , Hyangsook LEE , Sanghyun JO , Seunggeol NAM , Taehwan MOON , Hagyoul BAE , Eunha LEE , Junho LEE
摘要： An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.
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公开(公告)号：US20220351776A1
公开(公告)日：2022-11-03
申请号：US17540675
申请日：2021-12-02
发明人： Seunggeol NAM , Jinseong HEO , Taehwan MOON , Hagyoul BAE
IPC分类号： G11C15/04
摘要： Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.
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公开(公告)号：US20240266445A1
公开(公告)日：2024-08-08
申请号：US18638923
申请日：2024-04-18
发明人： Jinseong HEO , Taehwan MOON , Hagyoul BAE , Seunggeol NAM , Sangwook KIM , Kwanghee LEE
CPC分类号： H01L29/86 , H10B69/00 , H10K10/50 , H10K19/00 , H10K19/201
摘要： A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.
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9.发明公开公开(公告)号：US20240265967A1
公开(公告)日：2024-08-08
申请号：US18621853
申请日：2024-03-29
发明人： Seunggeol NAM , Jinseong HEO , Taehwan MOON , Hagyoul BAE
IPC分类号： G11C15/04
CPC分类号： G11C15/046
摘要： Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.
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10.发明公开公开(公告)号：US20230141173A1
公开(公告)日：2023-05-11
申请号：US17983856
申请日：2022-11-09
发明人： Seunggeol NAM , Hagyoul BAE , Jinseong HEO
IPC分类号： H01L29/78 , H01L27/118 , H01L29/49 , H01L29/423 , H01L29/786
CPC分类号： H01L29/78391 , H01L27/11807 , H01L29/4908 , H01L29/42392 , H01L29/78645 , H01L29/78696 , H01L2027/11838
摘要： According to various example embodiments, a semiconductor element includes: a channel layer including a semiconductor material; a p-type semiconductor layer and an n-type semiconductor layer apart from each other with the channel layer therebetween, a paraelectric layer on a first area of the channel layer, a ferroelectric layer on a second area different from the first area of the channel area, and having a polarization state due to a voltage applied from an external source, a first gate electrode on the paraelectric layer, a second gate electrode on the ferroelectric layer, and an insulating layer between the first gate electrode and the second gate electrode, and electrically separating the first gate electrode and the second gate electrode from each other.
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