公开(公告)号：US20250157916A1

公开(公告)日：2025-05-15

申请号：US18651944

申请日：2024-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEMYUNG CHOI ,  KANG-ILL SEO

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Integrated circuit (IC) devices are provided. An IC device includes a back-end-of-line (BEOL) region that includes a first via and a second via on a first lower metal line and a second lower metal line, respectively. The BEOL region includes a first upper metal line coupled to the first lower metal line by the first via, and a second upper metal line coupled to the second lower metal line by the second via. The first upper metal line and the first via each include a first metal. The second upper metal line and the second via each include a second metal that is different from the first metal. Moreover, the second upper metal line is wider than the first upper metal line. Related methods of forming BEOL regions of IC devices are also provided.

公开(公告)号：US20230369111A1

公开(公告)日：2023-11-16

申请号：US17929833

申请日：2022-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEMYUNG CHOI ,  Janggeun Lee ,  Wonhyuk Hong ,  Kang-Ill Seo

IPC: H01L21/768 ,  H01L21/3065 ,  H01L23/532

CPC classification number: H01L21/76861 ,  H01L21/3065 ,  H01L23/53261 ,  H01L23/53247

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing an underlying structure including a first insulating layer and forming a first metal structure, a first adhesion pattern, and a second insulating layer thereon. The second insulating layer may be on a side surface of the first metal structure, the first metal structure may include a metal pattern and a second adhesion pattern between the first insulating layer and the metal pattern, and the first adhesion pattern contacts side surfaces of the metal pattern and the second adhesion pattern. The methods may also include forming a second metal structure on the first metal structure. The metal pattern may include a contact portion protruding upwardly beyond an upper surface of the second insulating layer or may include an upper surface recessed with respect to the upper surface of the second insulating layer.

公开(公告)号：US20240355727A1

公开(公告)日：2024-10-24

申请号：US18459894

申请日：2023-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEMYUNG CHOI ,  Kang -Ill Seo ,  Se Jung Park

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53266

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower metal wire, an upper metal wire on the lower metal wire, a metal via between the lower metal wire and the upper metal wire, the metal via including a lower surface and an upper surface that respectively contact the lower metal wire and the upper metal wire, and a barrier layer extending on a side surface of the metal via. An upper portion of the barrier layer may extend upwardly beyond a lower surface of the upper metal wire.

公开(公告)号：US20230352399A1

公开(公告)日：2023-11-02

申请号：US17822246

申请日：2022-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEMYUNG CHOI ,  KANG-ILL SEO ,  JANGGEUN LEE

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/768

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower metal via, an upper metal via, a lower metal wire comprising a lower surface contacting the lower metal via and an upper surface contacting the upper metal via, and an upper metal wire on the upper metal via. The upper metal via is between the lower metal wire and the upper metal wire, and each of the lower metal via, the lower metal wire and the upper metal via comprises ruthenium (Ru) or molybdenum (Mo).