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1.发明公开公开(公告)号：US20230352405A1
公开(公告)日：2023-11-02
申请号：US17820949
申请日：2022-08-19
发明人： Janggeun Lee , Jaemyung Choi , Wonhyuk Hong , Kang-ill Seo
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5283 , H01L23/5226 , H01L21/76819 , H01L23/53295 , H01L23/53228 , H01L23/53257
摘要： Integrated circuit devices are provided. An integrated circuit device includes a first insulating layer and a metal via that is in the first insulating layer. The integrated circuit device includes a second insulating layer on the first insulating layer. The integrated circuit device includes a conductive material that is between sidewalls of the second insulating layer and on the metal via. Moreover, the integrated circuit device includes a metal line that is on the conductive material and/or the second insulating layer. Related methods of forming integrated circuit devices are also provided.
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公开(公告)号：US20230361032A1
公开(公告)日：2023-11-09
申请号：US17969440
申请日：2022-10-19
发明人： Wonhyuk HONG , Jaemyung Choi , Jaejik Baek , Janggeun Lee , Myunghoon Jung , Taesun Kim , Kang-ill Seo
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/5283 , H01L21/76885 , H01L21/76865 , H01L23/5226
摘要： A semiconductor device includes a dielectric layer, a plurality of vias formed in the dielectric layer, an adhesion layer deposited on a top surface of the dielectric layer, and a plurality of metal lines. A first metal line of the plurality of metal lines includes a first recess formed at a bottom surface of the first metal line such that a first section of the first metal line directly contacts the first via and a second section of the first metal line defined by the first recess does not directly contact the first via or the dielectric layer in which the first via is formed.
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3.发明公开公开(公告)号：US20230352400A1
公开(公告)日：2023-11-02
申请号：US17880554
申请日：2022-08-03
发明人： Tae Sun Kim , Janggeun Lee , Jaemyung Choi , Kang-ill Seo
IPC分类号： H01L23/522 , H01L23/532 , H01L21/768
CPC分类号： H01L23/5226 , H01L23/53228 , H01L23/53257 , H01L21/76885
摘要： Integrated circuit devices are provided. An integrated circuit device includes an insulating layer and a metal via structure that is in the insulating layer. The metal via structure has a lower portion and an upper portion that is narrower than the lower portion. Moreover, the integrated circuit device includes a metal line that is on and electrically connected to the metal via structure. Related methods of forming integrated circuit devices are also provided.
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4.发明公开公开(公告)号：US20230369111A1
公开(公告)日：2023-11-16
申请号：US17929833
申请日：2022-09-06
发明人： JAEMYUNG CHOI , Janggeun Lee , Wonhyuk Hong , Kang-Ill Seo
IPC分类号： H01L21/768 , H01L21/3065 , H01L23/532
CPC分类号： H01L21/76861 , H01L21/3065 , H01L23/53261 , H01L23/53247
摘要： Integrated circuit devices and methods of forming the same are provided. The methods may include providing an underlying structure including a first insulating layer and forming a first metal structure, a first adhesion pattern, and a second insulating layer thereon. The second insulating layer may be on a side surface of the first metal structure, the first metal structure may include a metal pattern and a second adhesion pattern between the first insulating layer and the metal pattern, and the first adhesion pattern contacts side surfaces of the metal pattern and the second adhesion pattern. The methods may also include forming a second metal structure on the first metal structure. The metal pattern may include a contact portion protruding upwardly beyond an upper surface of the second insulating layer or may include an upper surface recessed with respect to the upper surface of the second insulating layer.
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公开(公告)号：US20230275021A1
公开(公告)日：2023-08-31
申请号：US17738393
申请日：2022-05-06
发明人： BYOUNGHAK HONG , Jeonghyuk Yim , Inchan Hwang , Gilhwan Son , Seungyoung Lee , Saehan Park , Janggeun Lee , Myunghoon Jung , Seungchan Yun , Buhyun Ham , Kang-ILL Seo
IPC分类号： H01L23/528 , H01L23/522 , H01L21/302 , H01L21/8234
CPC分类号： H01L23/5286 , H01L23/5283 , H01L23/5226 , H01L21/302 , H01L21/823475
摘要： Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.
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