公开(公告)号：US20240006233A1

公开(公告)日：2024-01-04

申请号：US17855433

申请日：2022-06-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Kang FU ,  Hsien-Chang WU ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76843 ,  H01L23/5226 ,  H01L23/53247 ,  H01L23/53252 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877

摘要： A semiconductor device includes a substrate, an interconnect layer disposed over the substrate, a metal line formed in the interconnect layer, a dielectric layer disposed on the interconnect layer, and a via contact formed in the dielectric layer and electrically connected to the metal line. One of the via contact and the metal line includes a first metal material and a barrier metal layer disposed on the first metal material. The first metal material includes an alloy which is a mixture of two metal elements. The barrier metal layer includes one of the two metal elements.

公开(公告)号：US20180053725A1

公开(公告)日：2018-02-22

申请号：US15239198

申请日：2016-08-17

申请人： International Business Machines Corporation

发明人： Daniel C. Edelstein ,  Chih-Chao Yang

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L23/528 ,  H01L23/522 ,  H01L21/321

CPC分类号： H01L23/53238 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53247 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266

摘要： A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. The set of features have a first dimension. An adhesion promoting layer disposed over the patterned dielectric is deposited. A ruthenium layer disposed over the adhesion promoting layer is deposited. A cobalt layer is deposited over the ruthenium layer. A high temperature thermal anneal is performed which creates a ruthenium cobalt alloy layer to cover surfaces of the set of features. A metal layer is deposited disposed over the ruthenium cobalt alloy layer to form a set of metal conductor structures. In another aspect of the invention, a device is created using the method.

公开(公告)号：US20170092855A1

公开(公告)日：2017-03-30

申请号：US15375457

申请日：2016-12-12

申请人： Micron Technology, Inc.

发明人： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC分类号： H01L45/00

CPC分类号： H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

公开(公告)号：US20150203351A1

公开(公告)日：2015-07-23

申请号：US14595543

申请日：2015-01-13

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： GUANGCAI FU ,  TIANLUN YANG ,  XIAOPING ZHANG

IPC分类号： B81C1/00 ,  B81B7/00

CPC分类号： H01L23/5283 ,  B81B7/007 ,  B81B2201/0264 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00849 ,  B81C2201/0132 ,  H01L21/02068 ,  H01L21/475 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53247 ,  H01L29/0649 ,  H01L2221/1063

摘要： Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top surface coplanar with a top surface of the semiconductor substrate. A sacrificial layer is formed on the semiconductor substrate and the first electrode layer. A first mask layer made of a conductive material is formed on the sacrificial layer. The first mask layer and the sacrificial layer are etched until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer. A cleaning process is performed to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings. Conductive plugs are formed in the openings after the cleaning process.

摘要翻译： 提供了半导体器件和制造方法。 在半导体器件中，半导体衬底包括具有与半导体衬底的顶表面共面的顶表面的第一电极层。 在半导体衬底和第一电极层上形成牺牲层。 在牺牲层上形成由导电材料制成的第一掩模层。 蚀刻第一掩模层和牺牲层直到暴露第一​​电极层的表面以形成穿过第一掩模层和牺牲层的开口。 执行清洁处理以去除粘附到第一掩模层的表面并附着到开口的侧壁和底表面上的蚀刻副产物。 在清洁过程之后，在开口中形成导电塞。

公开(公告)号：US08970010B2

公开(公告)日：2015-03-03

申请号：US13834196

申请日：2013-03-15

申请人： Cree, Inc.

发明人： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

摘要： Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

摘要翻译： 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。

公开(公告)号：US20140264868A1

公开(公告)日：2014-09-18

申请号：US13834196

申请日：2013-03-15

申请人： CREE, INC.

发明人： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

摘要： Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

摘要翻译： 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。

公开(公告)号：US08716737B2

公开(公告)日：2014-05-06

申请号：US13530396

申请日：2012-06-22

申请人： Hsiu Jen Lin ,  Jian Shian Lin ,  Shau Yi Chen ,  Chieh Lung Lai

发明人： Hsiu Jen Lin ,  Jian Shian Lin ,  Shau Yi Chen ,  Chieh Lung Lai

IPC分类号： H01L33/00 ,  H01L21/00 ,  H01L23/532 ,  H01L23/00 ,  H01L33/30 ,  H01L33/40 ,  H01L33/48 ,  H01L33/62

CPC分类号： H01L23/53247 ,  H01L24/29 ,  H01L24/83 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/30 ,  H01L33/40 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/83193 ,  H01L2224/83207 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2933/0066 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/00014

摘要： An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics.

摘要翻译： LED包括第一金属间层，第一金属薄膜层，LED芯片，基板，第二金属薄膜层和第二金属间层。 第一金属薄膜层位于第一金属间层上。 LED芯片位于第一金属薄膜层上。 第二金属薄膜层位于基板上。 第二金属间化合物层位于第二金属薄膜层上，第一金属间化合物层位于第二金属间层上。 第一和第二金属薄膜层的材料选自由Au，Ag，Cu和Ni组成的组。 金属间层的材料选自Cu-In-Sn金属间化合物，Ni-In-Sn金属间化合物，Ni-Bi金属间化合物，Au-In金属间化合物，Ag-In金属间化合物，Ag-Sn 金属间化合物和Au-Bi金属间化合物。

公开(公告)号：US08524599B2

公开(公告)日：2013-09-03

申请号：US13050725

申请日：2011-03-17

申请人： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

发明人： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC分类号： H01L21/4763

CPC分类号： H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

摘要翻译： 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和第一导电材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：US20120153483A1

公开(公告)日：2012-06-21

申请号：US12973281

申请日：2010-12-20

申请人： Rohan N. Akolkar ,  Florian Gstrein ,  Daniel J. Zierath

发明人： Rohan N. Akolkar ,  Florian Gstrein ,  Daniel J. Zierath

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L23/53261 ,  H01L21/3105 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53247 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a melting point between a melting point of copper and a melting point of tungsten. Forming includes depositing a layer of metal or compound within the opening and on an upper surface of the dielectric layer Preferably, the barrierless single-phase interconnect comprises cobalt or a cobalt containing compound. Thus, an interconnect structure, including a via and associated line, is made up of a single-phase metal or compound without the use of a different material between the interconnect and the underlying dielectric, thus improving electrical performance and reliability and further simplifying the interconnect formation process.

摘要翻译： 形成互连结构的方法和包括所述互连结构的集成电路。 该方法包括：在导电层上沉积介电层; 在所述电介质层中形成开口以暴露所述导电层; 形成包含熔点在铜的熔点和钨的熔点之间的金属或化合物的无障碍单相互连。 形成包括在开口内和介电层的上表面上沉积一层金属或化合物。优选地，无障碍单相互连包括钴或含钴化合物。 因此，包括通孔和相关线路的互连结构由单相金属或化合物构成，而不需要在互连和下面的电介质之间使用不同的材料，从而改善电性能和可靠性并进一步简化互连 形成过程。

公开(公告)号：US20070228575A1

公开(公告)日：2007-10-04

申请号：US11758279

申请日：2007-06-05

申请人： Kazuyoshi INOUE

发明人： Kazuyoshi INOUE

IPC分类号： H01L23/49

CPC分类号： C22C5/08 ,  C22C5/06 ,  C22C9/00 ,  C22C9/06 ,  G02F2001/136295 ,  H01B1/02 ,  H01B1/026 ,  H01L21/2855 ,  H01L21/86 ,  H01L23/49866 ,  H01L23/53247 ,  H01L29/458 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A wiring material for TFT-LCD which comprises an Ag alloy containing Ag and Zr as essential components and further one or more metals selected from the group consisting of Au, Ni, Co and Al; and a wiring material which comprises a Cu alloy comprising Au and/or Co and Cu, wherein the alloy has a Cu content of 80 to 99.5 wt % and a sum of a Au (or Cu) on a glass substrate or a silicon wafer by the sputtering method has exhibited satisfactorily low electric resistance and also satisfactorily high adhesion strength to the substrate or the wafer.

摘要翻译： 一种用于TFT-LCD的布线材料，其包含含有Ag和Zr作为必要成分的Ag合金，还包括一种或多种选自Au，Ni，Co和Al的金属; 以及包含Au和/或Co和Cu的Cu合金的配线材料，其中，所述合金的Cu含量为80〜99.5重量％，玻璃基板或硅晶片上的Au（或Cu）的和为 溅射法表现出令人满意的低电阻，并且对基板或晶片的粘附强度也令人满意。