公开(公告)号：US10600729B2

公开(公告)日：2020-03-24

申请号：US16359307

申请日：2019-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong Soon Cho ,  Jae Eun Lee

IPC: H01L21/70 ,  H01L23/50 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

Abstract: A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

公开(公告)号：US20180090583A1

公开(公告)日：2018-03-29

申请号：US15473143

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Seok Choi ,  Ryuji Tomita ,  Joon Gon Lee ,  Chul Sung Kim ,  Jae Eun Lee

IPC: H01L29/45 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/485 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.

公开(公告)号：US10262933B2

公开(公告)日：2019-04-16

申请号：US15795448

申请日：2017-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong Soon Cho ,  Jae Eun Lee

IPC: H01L21/70 ,  H01L23/50

Abstract: A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

公开(公告)号：US11063036B2

公开(公告)日：2021-07-13

申请号：US15683050

申请日：2017-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Seok Choi ,  Chul Sung Kim ,  Jae Eun Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L23/485 ,  H01L27/06 ,  H01L49/02 ,  H01L29/775 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a first recess formed in the substrate, a first source/drain filling the first recess, a vertical metal resistor on the first source/drain, and an insulating liner separating the metal resistor from the first source/drain, with the vertical metal resistor being between two gate electrodes.

公开(公告)号：US10332984B2

公开(公告)日：2019-06-25

申请号：US15473143

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Seok Choi ,  Ryuji Tomita ,  Joon Gon Lee ,  Chul Sung Kim ,  Jae Eun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L21/84 ,  H01L27/12

Abstract: A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.