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    System on chip and electronic device including the same
    1.
    发明授权
    System on chip and electronic device including the same 有权

    公开(公告)号：US12181950B2

    公开(公告)日：2024-12-31

    申请号：US17943857

    申请日：2022-09-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungchul Jeon ,  Jae Min Kim ,  Hyunseok Kim ,  Junho Huh

    IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3296 ,  H03K17/687

    Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

    Multi-core system and controlling operation of the same
    2.
    发明授权
    Multi-core system and controlling operation of the same 有权

    公开(公告)号：US11734067B2

    公开(公告)日：2023-08-22

    申请号：US16789602

    申请日：2020-02-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Min Kim ,  Byungchul Jeon ,  Junho Huh

    IPC: G06F9/48 ,  G06F9/50 ,  G06F1/3287 ,  G06F11/30 ,  G06F11/34

    CPC classification number: G06F9/4893 ,  G06F1/3287 ,  G06F9/505 ,  G06F11/3024 ,  G06F11/3423 ,  G06F2209/486

    Abstract: In a method of operating a multi-core system comprising a plurality of processor cores, a plurality of task stall information respectively corresponding to a plurality of tasks are provided by monitoring a task stall time with respect to each task. The task stall time indicates a time while the each task is suspended within a task active time, and the task active time indicates a time while a corresponding processor core is occupied by the each task. Task scheduling is performed based on the plurality of task stall information, and a fine-grained dynamic voltage and frequency scaling (DVFS) is performed based on the task scheduling. The plurality of tasks may be assigned to the plurality of processor cores based on load unbalancing, and the effects of the fine-grained DVFS may be increased to reduce the power consumption of the multi-core system.

    SYSTEM ON CHIP AND ELECTRONIC DEVICE INCLUDING THE SAME
    3.
    发明申请
    SYSTEM ON CHIP AND ELECTRONIC DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20210034138A1

    公开(公告)日：2021-02-04

    申请号：US16845661

    申请日：2020-04-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungchul Jeon ,  Jae Min Kim ,  Hyunseok Kim ,  Junho Huh

    IPC: G06F1/3287 ,  H03K17/687 ,  G06F1/3296

    Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

    System on chip and electronic device including the same
    5.
    发明授权
    System on chip and electronic device including the same 有权

    公开(公告)号：US11467652B2

    公开(公告)日：2022-10-11

    申请号：US16845661

    申请日：2020-04-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungchul Jeon ,  Jae Min Kim ,  Hyunseok Kim ,  Junho Huh

    IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3296 ,  H03K17/687

    Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

    SEMICONDUCTOR DESIGN AUTOMATION SYSTEM AND COMPUTING SYSTEM INCLUDING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DESIGN AUTOMATION SYSTEM AND COMPUTING SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220138397A1

    公开(公告)日：2022-05-05

    申请号：US17395594

    申请日：2021-08-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Song-Yi Han ,  Jae Min Kim ,  Jae Ho Kim ,  Ji-Seong Doh ,  Kang-Hyun Baek ,  Young Kyou Shin ,  Seong Hun Jang ,  Young Jun Cho ,  Yun Ji Choi

    IPC: G06F30/398 ,  G06F30/12

    Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

    SYSTEM ON CHIP AND ELECTRONIC DEVICE INCLUDING THE SAME
    9.
    发明申请
    SYSTEM ON CHIP AND ELECTRONIC DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230004210A1

    公开(公告)日：2023-01-05

    申请号：US17943857

    申请日：2022-09-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungchul JEON ,  Jae Min Kim ,  Hyunseok Kim ,  Junho Huh

    IPC: G06F1/3287 ,  G06F1/3296 ,  H03K17/687

    Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

    Authentication circuit, electronic system including the same, and method of forming network
    10.
    发明授权
    Authentication circuit, electronic system including the same, and method of forming network 有权

    公开(公告)号：US11176259B2

    公开(公告)日：2021-11-16

    申请号：US16357841

    申请日：2019-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Min Kim ,  Jae Won Lee ,  Junho Huh

    IPC: G06F21/60 ,  G06F16/182 ,  H04L9/08 ,  H04L9/32 ,  H04L9/06

    Abstract: An electronic system includes a plurality of hardware devices and an authenticated circuit. The authenticated circuit is integrated, as fixed hardware, in the electronic system together with the plurality of hardware devices during a manufacturing process of the electronic system, the authenticated circuit configured to verify system integrity based on a system identification code provided from inside of the electronic system by at least one of the plurality of hardware devices, the system integrity indicating that a combination of the authenticated circuit and the plurality of hardware devices has not been modified since the manufacturing process, the authenticated circuit configured to perform a mining operation to generate a next block, the next block to be linked to a blockchain only in response to the authenticated circuit verifying the system integrity. Indiscriminate mining competition may be prevented or reduced in likelihood of occurrence.

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