公开(公告)号：US11687696B2

公开(公告)日：2023-06-27

申请号：US17395594

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song-Yi Han ,  Jae Min Kim ,  Jae Ho Kim ,  Ji-Seong Doh ,  Kang-Hyun Baek ,  Young Kyou Shin ,  Seong Hun Jang ,  Young Jun Cho ,  Yun Ji Choi

IPC: G06F30/398 ,  G06F30/12 ,  G06F119/02

CPC classification number: G06F30/398 ,  G06F30/12 ,  G06F2119/02

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

公开(公告)号：US20220138397A1

公开(公告)日：2022-05-05

申请号：US17395594

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song-Yi Han ,  Jae Min Kim ,  Jae Ho Kim ,  Ji-Seong Doh ,  Kang-Hyun Baek ,  Young Kyou Shin ,  Seong Hun Jang ,  Young Jun Cho ,  Yun Ji Choi

IPC: G06F30/398 ,  G06F30/12

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

公开(公告)号：US12182490B2

公开(公告)日：2024-12-31

申请号：US18316405

申请日：2023-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song-Yi Han ,  Jae Min Kim ,  Jae Ho Kim ,  Ji-Seong Doh ,  Kang-Hyun Baek ,  Young Kyou Shin ,  Seong Hun Jang ,  Young Jun Cho ,  Yun Ji Choi

IPC: G06F30/398 ,  G06F30/12 ,  G06F119/02

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

公开(公告)号：US20230281375A1

公开(公告)日：2023-09-07

申请号：US18316405

申请日：2023-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song-Yi Han ,  Jae Min Kim ,  Jae Ho Kim ,  Ji-Seong Doh ,  Kang-Hyun Baek ,  Young Kyou Shin ,  Seong Hun Jang ,  Young Jun Cho ,  Yun Ji Choi

IPC: G06F30/398 ,  G06F30/12

CPC classification number: G06F30/398 ,  G06F30/12 ,  G06F2119/02

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

公开(公告)号：US20180331201A1

公开(公告)日：2018-11-15

申请号：US16026749

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3205 ,  H01L29/51

CPC classification number: H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.