公开(公告)号：US20150194438A1

公开(公告)日：2015-07-09

申请号：US14450854

申请日：2014-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Soo Kim ,  Dong-Soo Woo ,  Se-myeong Jang

IPC: H01L27/115

CPC classification number: H01L27/10891 ,  H01L27/10876

Abstract: A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.

Abstract translation: 半导体器件可以包括：衬底，其包括在第一方向上具有长轴和在第二方向上具有短轴的多个有源区，所述多个有源区沿着所述第一和第二方向重复且分开地定位;隔离膜 限定多个有源区域，跨越多个有源区域和隔离膜延伸的多个字线，以及分别覆盖多个字线的至少一部分的正固定电荷含有层。

公开(公告)号：US20130344666A1

公开(公告)日：2013-12-26

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。

公开(公告)号：US09685519B2

公开(公告)日：2017-06-20

申请号：US14728328

申请日：2015-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Na-Ra Kim ,  Seung-Hwan Kim ,  Sung-Hee Lee ,  Dae-Sin Kim ,  Ji-Young Kim ,  Dong-Soo Woo

IPC: H01L29/66 ,  H01L21/332 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108 ,  H01L21/762 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/76229 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/407 ,  H01L29/7827 ,  H01L29/785

Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.

公开(公告)号：US09536884B2

公开(公告)日：2017-01-03

申请号：US14450854

申请日：2014-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Soo Kim ,  Dong-Soo Woo ,  Se-myeong Jang

IPC: H01L27/115 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10876

Abstract: A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.

Abstract translation: 半导体器件可以包括：衬底，其包括在第一方向上具有长轴和在第二方向上具有短轴的多个有源区，所述多个有源区沿着所述第一和第二方向重复且分开地定位;隔离膜 限定多个有源区域，跨越多个有源区域和隔离膜延伸的多个字线，以及分别覆盖多个字线的至少一部分的正固定电荷含有层。

公开(公告)号：US09082850B2

公开(公告)日：2015-07-14

申请号：US13959765

申请日：2013-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Na-Ra Kim ,  Seung-Hwan Kim ,  Sung-Hee Lee ,  Dae-Sin Kim ,  Ji-Young Kim ,  Dong-Soo Woo

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L29/4236 ,  H01L21/76229 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/407 ,  H01L29/7827 ,  H01L29/785

Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.

Abstract translation: 半导体器件包括在衬底中的场区域以限定有源区域，栅极沟槽包括跨过有源区域设置的有源沟槽和场区域中的场沟槽，以及填充栅极沟槽并在第一方向上延伸的字线。 字线包括占据有源沟槽的有源栅电极和占据场沟的场栅电极。 设置在彼此相邻并且在其间具有一个字线的有源区之间的每个场栅电极的底表面被设置在比有源栅电极的底表面更高的电平。

公开(公告)号：US08835252B2

公开(公告)日：2014-09-16

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。