公开(公告)号：US11856753B2

公开(公告)日：2023-12-26

申请号：US17837962

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jung Lee ,  Joon-Seok Moon ,  Dongsoo Woo

IPC: H10B12/00 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H10B12/34 ,  H01L21/28088 ,  H01L21/32133 ,  H01L29/0649 ,  H01L29/4966 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

公开(公告)号：US10964704B2

公开(公告)日：2021-03-30

申请号：US16550192

申请日：2019-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jung Lee ,  Joon-Seok Moon ,  Dongsoo Woo

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49

Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

公开(公告)号：US20130344666A1

公开(公告)日：2013-12-26

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。

公开(公告)号：US08835252B2

公开(公告)日：2014-09-16

申请号：US13902202

申请日：2013-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Seok Moon ,  Jae-Rok Kahng ,  Hyun-Seung Song ,  Dong-Soo Woo ,  Sang-Hyun Lee ,  Hyun-Jung Lee

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/788

CPC classification number: H01L29/788 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Abstract translation: 提供制造半导体器件的方法包括在有源区的第一至​​第三表面上形成第一至第三硅结晶层; 去除所述第一硅晶层以暴露所述第一表面; 在暴露的第一表面上形成位线堆叠; 在所述位线堆叠的两个侧表面上形成位线侧壁间隔物以与所述有源区域的所述第二和第三硅结晶层的部分垂直对准; 去除设置在位线侧壁间隔物下方的第二和第三硅结晶层，以暴露有源区的第二和第三表面; 以及形成与所述有源区域的第二和第三表面接触的存储接触插塞。

公开(公告)号：US11380690B2

公开(公告)日：2022-07-05

申请号：US17186936

申请日：2021-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jung Lee ,  Joon-Seok Moon ,  Dongsoo Woo

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49

Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

公开(公告)号：US10424649B2

公开(公告)日：2019-09-24

申请号：US16026097

申请日：2018-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Seok Moon ,  Dong Sik Kong ,  Sung Won Yoo ,  Hee Sun Joo ,  Kyo-Suk Chae

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108

Abstract: A semiconductor device includes a substrate, device isolation film defining an active region of the substrate in which a gate trench extends, a gate insulating film disposed along sides and a bottom of the gate trench, a gate electrode disposed on the gate insulating film in the gate trench and having a first portion, a second portion on the first portion, and a third portion on the second portion, a first barrier film pattern interposed between the first portion of the gate electrode and the gate insulating film, a second barrier film pattern interposed between the second portion of the gate electrode and the gate insulating film, and a third barrier film pattern interposed between the third portion of the gate electrode and the gate insulating film. The work function of the first barrier film pattern is greater than the work function of the second barrier film pattern and less than the work function of the third barrier film pattern.

公开(公告)号：US09224619B2

公开(公告)日：2015-12-29

申请号：US14502345

申请日：2014-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seol-Min Yi ,  Dae-Hyun Moon ,  Joon-Seok Moon ,  Se-Keun Park ,  Hyeoung-Won Seo

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/423 ,  H01L27/108 ,  H01L27/22 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/32133 ,  H01L21/28088 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/228 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966

Abstract: The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.

Abstract translation: 半导体器件包括衬底，形成在衬底中的沟槽，保形地形成在沟槽的内表面上的栅极绝缘层，形成在栅极绝缘层上并填充沟槽的一部分的掩埋栅电极和形成的覆盖层 在掩埋的栅极电极上并填充沟槽。 掩埋栅电极包括第一栅电极和围绕第一栅电极的底部的第二栅电极，并且在第一栅电极的顶部与栅极绝缘层之间设置气隙。