公开(公告)号：US09798469B2

公开(公告)日：2017-10-24

申请号：US14662736

申请日：2015-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： YoungWook Kim ,  Kui-Yon Mun ,  Soong-Mann Shin ,  Jae-Sung Yu

IPC: G06F3/06 ,  G11C16/04 ,  G11C7/04

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G11C7/04 ,  G11C16/0466

Abstract: A storage device includes a nonvolatile memory and a memory controller. The nonvolatile memory performs read, write, and erase operations. The memory controller operates in an operating mode where the memory controller exchanges a voltage signal, set to a reference voltage level within an allowable range, with the nonvolatile memory or receives the voltage signal from an external device. When operating in the operating mode, the memory controller optimizes an operating frequency of the nonvolatile memory depending on a voltage level of the voltage signal and a temperature.

公开(公告)号：US20160239220A1

公开(公告)日：2016-08-18

申请号：US14994168

申请日：2016-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Sung Yu ,  Kui-Yon Mun ,  Youngwook Kim

IPC: G06F3/06 ,  G11C29/56 ,  G11C8/18

CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1689 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C29/56004

Abstract: A storage device includes a memory device configured to store data and a memory controller connected to the memory device through a data strobe line and a plurality of data lines. The storage device adds a predetermined specific pattern in front of data and processes data input following the specific pattern as valid data during a read or write operation. The specific pattern is provided in alignment with a data strobe signal (DQS) latency cycle. The memory controller detects a specific pattern input from the memory device during a read operation and processes data input following the specific pattern as valid data when the detected specific pattern matches an internally stored specific pattern.

Abstract translation: 存储装置包括被配置为存储数据的存储器件和通过数据选通线和多条数据线连接到存储器件的存储器控​​制器。 存储装置在数据前面增加预定的特定模式，并且在读取或写入操作期间将跟随特定模式输入的数据作为有效数据进行处理。 提供特定模式与数据选通信号（DQS）延迟周期对齐。 存储器控制器在读取操作期间检测来自存储器件的特定模式输入，并且当检测到的特定模式与内部存储的特定模式匹配时，将特定模式之后的数据输入作为有效数据进行处理。

公开(公告)号：US10095420B2

公开(公告)日：2018-10-09

申请号：US14994168

申请日：2016-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Sung Yu ,  Kui-Yon Mun ,  Youngwook Kim

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G11C29/56 ,  G11C29/02

Abstract: A storage device includes a memory device configured to store data and a memory controller connected to the memory device through a data strobe line and a plurality of data lines. The storage device adds a predetermined specific pattern in front of data and processes data input following the specific pattern as valid data during a read or write operation. The specific pattern is provided in alignment with a data strobe signal (DQS) latency cycle. The memory controller detects a specific pattern input from the memory device during a read operation and processes data input following the specific pattern as valid data when the detected specific pattern matches an internally stored specific pattern.