公开(公告)号：US11728245B2

公开(公告)日：2023-08-15

申请号：US17316970

申请日：2021-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jubin Seo ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park ,  Sujeong Park ,  Jaewon Hwang

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/53209 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

公开(公告)号：US11342221B2

公开(公告)日：2022-05-24

申请号：US16741187

申请日：2020-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Hwang ,  Jinnam Kim ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306

Abstract: Aspects of the present disclosure are related to a semiconductor device that includes a crystalline substrate having a first surface and a second surface vertically opposite each other and an insulating layer disposed on the first surface of the crystalline substrate. The device may also include an etch stop layer interposed between and contacting the crystalline substrate and the insulating layer and a conductive through via structure penetrating the crystalline substrate and the insulating layer. The device may also include an insulating separation layer disposed horizontally adjacent to the conductive through via structure, and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive through via structure and the crystalline substrate, and a second portion disposed between the conductive through via structure and the etch stop layer.

公开(公告)号：US20210066123A1

公开(公告)日：2021-03-04

申请号：US16741187

申请日：2020-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Hwang ,  Jinnam Kim ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/02

Abstract: Aspects of the present disclosure are related to a semiconductor device that includes a crystalline substrate having a first surface and a second surface vertically opposite each other and an insulating layer disposed on the first surface of the crystalline substrate. The device may also include an etch stop layer interposed between and contacting the crystalline substrate and the insulating layer and a conductive through via structure penetrating the crystalline substrate and the insulating layer. The device may also include an insulating separation layer disposed horizontally adjacent to the conductive through via structure, and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive through via structure and the crystalline substrate, and a second portion disposed between the conductive through via structure and the etch stop layer.

公开(公告)号：US11600553B2

公开(公告)日：2023-03-07

申请号：US17381287

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungjoo Park ,  Jaewon Hwang ,  Kwangjin Moon ,  Kunsang Park

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.

公开(公告)号：US11101196B2

公开(公告)日：2021-08-24

申请号：US16795686

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungjoo Park ,  Jaewon Hwang ,  Kwangjin Moon ,  Kunsang Park

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.

公开(公告)号：US11908775B2

公开(公告)日：2024-02-20

申请号：US17645472

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Hwang ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L23/481 ,  H01L23/535 ,  H01L24/29 ,  H01L24/45

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

公开(公告)号：US12249558B2

公开(公告)日：2025-03-11

申请号：US18341087

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jubin Seo ,  Kwangjin Moon ,  Kunsang Park ,  Myungjoo Park ,  Sujeong Park ,  Jaewon Hwang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.

公开(公告)号：US20220359348A1

公开(公告)日：2022-11-10

申请号：US17645472

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Hwang ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/485 ,  H01L23/535 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.