Abstract:
A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.
Abstract:
Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.
Abstract:
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.
Abstract:
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.
Abstract:
A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern.
Abstract:
Aspects of the present disclosure are related to a semiconductor device that includes a crystalline substrate having a first surface and a second surface vertically opposite each other and an insulating layer disposed on the first surface of the crystalline substrate. The device may also include an etch stop layer interposed between and contacting the crystalline substrate and the insulating layer and a conductive through via structure penetrating the crystalline substrate and the insulating layer. The device may also include an insulating separation layer disposed horizontally adjacent to the conductive through via structure, and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive through via structure and the crystalline substrate, and a second portion disposed between the conductive through via structure and the etch stop layer.
Abstract:
Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.
Abstract:
Aspects of the present disclosure are related to a semiconductor device that includes a crystalline substrate having a first surface and a second surface vertically opposite each other and an insulating layer disposed on the first surface of the crystalline substrate. The device may also include an etch stop layer interposed between and contacting the crystalline substrate and the insulating layer and a conductive through via structure penetrating the crystalline substrate and the insulating layer. The device may also include an insulating separation layer disposed horizontally adjacent to the conductive through via structure, and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive through via structure and the crystalline substrate, and a second portion disposed between the conductive through via structure and the etch stop layer.
Abstract:
Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.
Abstract:
Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.