公开(公告)号：US09793155B2

公开(公告)日：2017-10-17

申请号：US14734287

申请日：2015-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jun Seong ,  Jee-hoon Han

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11531 ,  H01L21/033 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L21/768 ,  H01L21/0337 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes a pad portion and a line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as a mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. A lower mask pattern including at least one line mask, bridge mask, and pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.