公开(公告)号：US20220302157A1

公开(公告)日：2022-09-22

申请号：US17351486

申请日：2021-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeyong KIM ,  Junghwan LEE

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A through via structure includes a through via and a capping pattern. The through via includes a metal pattern extending in a vertical direction, and a barrier pattern on a sidewall and a lower surface of the metal pattern. The capping pattern contacts an upper surface of the through via. A lowermost surface of an edge portion of the capping pattern is not higher than a lowermost surface of a central portion of the capping pattern.

公开(公告)号：US20240123265A1

公开(公告)日：2024-04-18

申请号：US18518189

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunah KIM ,  Seonuk NA ,  Joonhyoung KIM ,  Jeeyong KIM ,  Hyojin KIM ,  Youngchal PARK ,  Hyeongjoon SEO ,  Youngtae SONG ,  Kisup LEE ,  Sanghoon LEE ,  Sungjune CHO ,  Sungjin CHO ,  Younglae JO ,  Wangbyung CHAE

IPC: A62B18/00 ,  A62B9/00 ,  A62B18/10 ,  A62B23/02

CPC classification number: A62B18/003 ,  A62B9/006 ,  A62B18/10 ,  A62B23/02

Abstract: A mask and a controlling method thereof are disclosed. The mask includes a fan that provides an air volume to an inside of the mask, a valve that discharges air from the mask, a pressure sensor, and a processor. The processor may control the pressure sensor to detect a maximum pressure value and a minimum pressure value inside the mask worn by a user. The processor may identify a time for a single breath based on a maximum pressure value and a minimum pressure value detected at the pressure sensor. The processor may identify a number of breaths based on the identified time for the single breath and a predetermined time. The processor may control the fan to provide an air volume set at a level corresponding to the identified number of breaths among a plurality of levels divided based on a predetermined number of breaths.

公开(公告)号：US20230232628A1

公开(公告)日：2023-07-20

申请号：US17963320

申请日：2022-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Subin SHIN ,  Sangwon KIM ,  Jeeyong KIM ,  Hyeonjoo SONG ,  Habin LIM

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/5283

Abstract: A semiconductor device includes a stack structure having gate electrodes and interlayer insulating layers, the stack structure having a cell region and a step region, and the gate electrodes extending in a first direction to have a step shape in the step region, channel structures through the stack structure in the cell region, separation structures through the stack structure and extending in the first direction, and support structures between the separation structures and through the stack structure in the step region. The step region includes first and second regions, the first region closer to the cell region in the first direction than the second region is, the support structures include first and second support structures through the stack structure in the first and second regions, respectively, a maximum width of the first support structure being greater than that of the second support structure.

公开(公告)号：US20230042792A1

公开(公告)日：2023-02-09

申请号：US17714412

申请日：2022-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghui HONG ,  Sangwon KIM ,  Jeeyong KIM ,  Subin SHIN ,  Habin LIM

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A peripheral circuit structure may include peripheral circuits and peripheral circuit lines on a semiconductor substrate, a semiconductor layer including cell array and connection regions on the peripheral circuit structure, a stack including electrodes stacked on the semiconductor layer having a stepwise structure on the connection region, and a planarization insulating layer covering the stack, vertical structures on the cell array region penetrating the stack, including a data storage pattern, a dam group including insulating dams on the connection region penetrating the stack, penetration plugs penetrating the insulating dams and connected to respective peripheral circuit lines, the dam group including a first insulating dam farthest from the cell array region, the first insulating dam including first and second sidewall portions spaced apart, a difference between upper and lower thicknesses of the second sidewall portion of the first insulating dam is larger than that of the first sidewall portion.

公开(公告)号：US20220328515A1

公开(公告)日：2022-10-13

申请号：US17522175

申请日：2021-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeyong KIM ,  Shin Hum CHO ,  Joohyung KANG ,  Eunsong LEE

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes insulation patterns spaced apart from each other on a substrate in a first direction that is substantially perpendicular to an upper surface of the substrate, gate electrodes spaced apart from each other in the first direction, and a channel extending in the first direction through the insulation patterns and the gate electrodes on the substrate. Each insulation pattern may extend in a second direction that is parallel to the upper surface of the substrate. Each insulation pattern may include boron nitride (BN). Each gate electrode may extend in the second direction between neighboring insulation patterns.

公开(公告)号：US20130228934A1

公开(公告)日：2013-09-05

申请号：US13779174

申请日：2013-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeeyong KIM ,  Hyunchul Back ,  Jung-Hwan Lee ,  Hyunmin Lee

IPC: H01L23/48

CPC classification number: H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。