公开(公告)号：US20200243558A1

公开(公告)日：2020-07-30

申请号：US16845615

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Sunggil KIM ,  Seulye KIM ,  HongSuk KIM ,  Phil Ouk NAM ,  Jaeyoung AHN

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US20220139956A1

公开(公告)日：2022-05-05

申请号：US17578965

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Sunggil KIM ,  Seulye KIM ,  HongSuk KIM ,  Phil Ouk NAM ,  Jaeyoung AHN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/423 ,  H01L29/04 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/11524 ,  H01L27/11556

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US20190181226A1

公开(公告)日：2019-06-13

申请号：US16186915

申请日：2018-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Dongkyum KIM ,  Sunggil KIM ,  Seulye KIM ,  Sangsoo LEE ,  Hyeeun HONG

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.

公开(公告)号：US20180315770A1

公开(公告)日：2018-11-01

申请号：US15864410

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Sunggil KIM ,  Seulye KIM ,  HongSuk KIM ,  Phil Ouk NAM ,  Jaeyoung AHN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/04 ,  H01L29/792 ,  H01L29/423

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US20220384482A1

公开(公告)日：2022-12-01

申请号：US17881707

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan KIM ,  Sunggil KIM ,  Dongkyum KIM ,  Seulye KIM ,  Ji-Hoon CHOI

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/792 ,  H01L29/04 ,  H01L29/423 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US20210217771A1

公开(公告)日：2021-07-15

申请号：US17195756

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon CHOI ,  Sung-Gil KIM ,  Jung-Hwan KIM ,  Chan-Hyoung KIM ,  Woo-Sung LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

公开(公告)号：US20210043647A1

公开(公告)日：2021-02-11

申请号：US16838586

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan KIM ,  Sunggil KIM ,  Dongkyum KIM ,  Seulye KIM ,  Ji-Hoon CHOI

IPC: H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US20190006385A1

公开(公告)日：2019-01-03

申请号：US15987545

申请日：2018-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Gil KIM ,  Seul-Ye KIM ,  Hong-suk KIM ,  Phil-Ouk NAM ,  Jae-Young AHN ,  Ji-Hoon CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L27/11556 ,  H01L27/11575

Abstract: A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.