公开(公告)号：US20250120140A1

公开(公告)日：2025-04-10

申请号：US18743372

申请日：2024-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Oh

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a substrate; a fin-type active region that extends in a first horizontal direction on the substrate; a gate line on the fin-type active region, wherein the gate line extends in a second horizontal direction that intersects the first horizontal direction; and a gate dielectric film that is in contact with a lower surface and opposite sidewalls of the gate line, wherein a gate upper surface of the gate line includes a portion that has a decreasing distance from the substrate in a vertical direction as a distance between the portion of the gate upper surface of the gate line and the gate dielectric film in the first horizontal direction decreases.

公开(公告)号：US10186457B2

公开(公告)日：2019-01-22

申请号：US15794107

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Myung ,  GeumJung Seong ,  Jisoo Oh ,  JinWook Lee ,  Dohyoung Kim ,  Yong-Ho Jeon

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US09806168B2

公开(公告)日：2017-10-31

申请号：US14988867

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： GeumJung Seong ,  JinWook Lee ,  Dohyoung Kim ,  Sungwoo Myung ,  Jisoo Oh ,  Yong-Ho Jeon

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966

Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

公开(公告)号：US09806166B2

公开(公告)日：2017-10-31

申请号：US15401562

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Myung ,  GeumJung Seong ,  Jisoo Oh ,  JinWook Lee ,  Dohyoung Kim ,  Yong-Ho Jeon

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US10522401B2

公开(公告)日：2019-12-31

申请号：US16237948

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Myung ,  GeumJung Seong ,  Jisoo Oh ,  JinWook Lee ,  Dohyoung Kim ,  Yong-Ho Jeon

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.