公开(公告)号：US20190341358A1

公开(公告)日：2019-11-07

申请号：US16252810

申请日：2019-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YANG HEE LEE ,  Jong Hyuk Park ,  Jin Woo Bae ,  Choong Seob Shin ,  Hyo Jin Oh ,  Bo Un Yoon ,  Il Young Yoon ,  Hee Sook Cheon

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/02

Abstract: A method of forming a semiconductor device, includes: forming a design pattern on a substrate, wherein the design pattern protrudes from the substrate; forming a filling layer on the substrate, wherein the filling layer at least partially covers the design pattern; forming a polishing resistance pattern adjacent to the design pattern in the filling layer using a laser irradiation process and/or an ion implantation process; and removing the filling layer using a chemical mechanical polishing (CMP) process to expose the design pattern.

公开(公告)号：US11581318B2

公开(公告)日：2023-02-14

申请号：US17237195

申请日：2021-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Sung Park ,  Jong Hyuk Park ,  Jin Woo Bae ,  Bo Un Yoon ,  Il Young Yoon ,  Bong Sik Choi

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/027 ,  H01L23/544

Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

公开(公告)号：US10964751B2

公开(公告)日：2021-03-30

申请号：US16586140

申请日：2019-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hao Cui ,  Se Yun Park ,  Jong Hyuk Park ,  Bo Un Yoon ,  Il Young Yoon

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device that includes a plurality of word lines disposed on a substrate in which p-type and n-type active regions are defined, and extends in a first direction. A plurality of bit lines is disposed on the plurality of word lines and extends in a second direction, perpendicular to the first direction. A plurality of memory cells is disposed between the plurality of word lines and the plurality of bit lines and each includes a data storage pattern. The plurality of memory cells includes a plurality of dummy memory cells and a plurality of main memory cells. An upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells.

公开(公告)号：US10711160B2

公开(公告)日：2020-07-14

申请号：US15883655

申请日：2018-01-30

Applicant: Samsung Electronics Co., Ltd. ,  KCTECH CO., LTD.

Inventor： Seung Ho Park ,  Hyun Goo Kong ,  Jung Hun Kim ,  Sang Mi Lee ,  Woo In Lee ,  Hee Sook Cheon ,  Sang Kyun Kim ,  Hao Cui ,  Jong Hyuk Park ,  Il Young Yoon

IPC: H01L21/3205 ,  C09G1/02 ,  H01L21/28 ,  H01L21/321 ,  H01L27/108

Abstract: A slurry composition for polishing a metal layer and a method for fabricating a semiconductor device using the same are provided. The slurry composition for polishing a metal layer includes polishing particles including a metal oxide, an oxidizer including hydrogen peroxide, and a first polishing regulator including at least one selected from a group consisting of phosphate, phosphite, hypophosphite, and metaphosphate, wherein a content of the oxidizer is 0.01 wt % to 0.09 wt % with respect to 100 wt % of the slurry composition for polishing the metal layer.

公开(公告)号：US11011526B2

公开(公告)日：2021-05-18

申请号：US16564688

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Sung Park ,  Jong Hyuk Park ,  Jin Woo Bae ,  Bo Un Yoon ,  Il Young Yoon ,  Bong Sik Choi

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/544 ,  H01L21/027

Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.