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    Tunable radio frequency circuit, control method and electronic device including the same
    1.
    发明授权
    Tunable radio frequency circuit, control method and electronic device including the same 有权

    公开(公告)号：US11450935B2

    公开(公告)日：2022-09-20

    申请号：US16733473

    申请日：2020-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jonghyuk Kim ,  Hyoseok Na

    IPC: H01P1/203 ,  H01P1/213 ,  H01P1/212 ,  H03H7/38 ,  H03H7/01

    Abstract: An embodiment of the disclosure provides a tunable radio frequency (RF) circuit, a control method, and an electronic device including the same. An electronic device according to an embodiment of the disclosure may include an antenna, a transceiver, a tunable radio frequency (RF), and at least one processor operatively coupled with the transceiver and the tunable RF circuit. The tunable RF circuit may further include a switch, a low noise amplifier (LNA), a power amplifier (PA), a fixed filter configured to pass signals in a first frequency band, and attenuate signals in a second frequency band at least one tunable filter configured to pass signals in at least a portion of the second frequency band, where the portion of the second frequency band is tunable, and at least one detector configured to detect a signal strength passing through the at least one tunable filter.

    SEMICONDUCTOR MEMORY DEVICES HAVING ADJUSTABLE I/O SIGNAL LINE LOADING THAT SUPPORTS REDUCED POWER CONSUMPTION DURING READ AND WRITE OPERATIONS
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES HAVING ADJUSTABLE I/O SIGNAL LINE LOADING THAT SUPPORTS REDUCED POWER CONSUMPTION DURING READ AND WRITE OPERATIONS 审中-公开

    公开(公告)号：US20240105255A1

    公开(公告)日：2024-03-28

    申请号：US18322894

    申请日：2023-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Jun Lee ,  Sang-Yun Kim ,  Jonghyuk Kim ,  Bok-Yeon Won

    IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

    CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

    Abstract: A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n-1th connection control transistor is configured to electrically short the n-1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank. A control circuit is provided, which is configured to reduce I/O signal line power consumption within the memory device during read (and write) operations.

    SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20170103987A1

    公开(公告)日：2017-04-13

    申请号：US15237709

    申请日：2016-08-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehee Kim ,  Soonmok Ha ,  Jonghyuk Kim ,  Joonsoo Park

    IPC: H01L27/108

    CPC classification number: H01L27/10894 ,  H01L27/10814 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10879 ,  H01L27/10885 ,  H01L28/90

    Abstract: A method for manufacturing a semiconductor device includes forming first and second lower structures including selection elements on first and second chip regions of a substrate, respectively, forming first and second mold layers on the first and second lower structures, respectively, forming first and second support layers on the first and second mold layers, respectively, patterning the first support layer and the first mold layer to form first holes exposing the first lower structure, forming first lower electrodes in the first holes, forming a support pattern including at least one opening by selectively patterning the first support layer while leaving the second support layer, and removing the first mold layer through the opening. A top surface of the support pattern is disposed at a substantially same level as a top surface of the second support layer.

    Shield structure in electronic device and operation method thereof
    5.
    发明授权
    Shield structure in electronic device and operation method thereof 有权

    公开(公告)号：US12256486B2

    公开(公告)日：2025-03-18

    申请号：US18115992

    申请日：2023-03-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jonghyuk Kim ,  Sangdeok Lee ,  Woosung Choi

    IPC: H05K1/02 ,  H05K1/18 ,  H05K9/00

    Abstract: Various embodiments of the present disclosure relate to a package structure capable of allowing a shield used for noise attenuation to be used for other purposes, in an electronic device in which components are arranged at high density, and an operation method for preventing/reducing noise radiation or detecting in advance defects in a manufacturing process using the same. For this, an electronic device may include: a printed circuit board (PCB), and a package disposed on the printed circuit board. The package may include: a ground pad and at least one shield pad connected to the printed circuit board, a laminated structure comprising a plurality of laminated ground layers electrically connected to the ground pad by at least one via hole, at least one electronic component disposed on an uppermost surface of the plurality of laminated ground layers, a shield covering the at least one electronic component, wherein the at least one component is not exposed to the outside, and at least one switch device comprising a switch including a first terminal electrically connected to the shield through a first conductor wiring, a second terminal electrically connected to one of the plurality of ground layers through a second conductor wiring, and a third terminal electrically connected to the shield pad through a third conductor wiring and disposed on the uppermost surface and configured to selectively connect the first terminal to the second terminal or the third terminal wherein the shield is connected to one of the one ground layer or the shield pad.

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