公开(公告)号：US20230261079A1

公开(公告)日：2023-08-17

申请号：US17987126

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun SONG ,  Pilkwang KIM ,  Joohyung YOU ,  Sungmin KIM ,  Yonghee PARK ,  Young-Seok SONG ,  Takeshi OKAGAKI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0847 ,  H01L29/6656

Abstract: Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first and second regions, a device isolation pattern in the substrate, a lower separation dielectric pattern on the first region of the substrate, first channel patterns on the lower separation dielectric pattern, a first gate electrode on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.

公开(公告)号：US20230231026A1

公开(公告)日：2023-07-20

申请号：US17890547

申请日：2022-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungkyu KIM ,  Yonghee PARK ,  Dong-Gwan SHIN ,  Dae Sin KIM ,  Sangyong KIM ,  Joohyung YOU

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L29/6656 ,  H01L29/78696 ,  H01L29/0847

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.