公开(公告)号：US20240038763A1

公开(公告)日：2024-02-01

申请号：US18486331

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L2027/11829 ,  H01L2027/11851 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20230231026A1

公开(公告)日：2023-07-20

申请号：US17890547

申请日：2022-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungkyu KIM ,  Yonghee PARK ,  Dong-Gwan SHIN ,  Dae Sin KIM ,  Sangyong KIM ,  Joohyung YOU

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L29/6656 ,  H01L29/78696 ,  H01L29/0847

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.

公开(公告)号：US20240113182A1

公开(公告)日：2024-04-04

申请号：US18538575

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghee PARK ,  Myunggil KANG ,  Uihui KWON ,  Seungkyu KIM ,  Ahyoung KIM ,  Ahyoung KIM ,  Youngseok SONG

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

公开(公告)号：US20220165857A1

公开(公告)日：2022-05-26

申请号：US17352973

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghee PARK ,  Myunggil KANG ,  Uihui KWON ,  Seungkyu KIM ,  Ahyoung KIM ,  Youngseok SONG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

公开(公告)号：US20240266402A1

公开(公告)日：2024-08-08

申请号：US18393009

申请日：2023-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegon KIM ,  Jihye YI ,  Yonghee PARK ,  Sanghoon HAN

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/155 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device, including a substrate, a first active pattern on the substrate, a first channel pattern on the first active pattern, the first channel pattern including a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern, a first source/drain pattern connected to the first channel pattern, and a gate electrode on the first channel pattern, wherein each of the first semiconductor pattern and the second semiconductor pattern includes a plurality of semiconductor layers, and at least one superlattice layer between adjacent semiconductor layers among the plurality of semiconductor layers, wherein the at least one superlattice layer included in the first semiconductor pattern has a first length, wherein the at least one superlattice layer included in the second semiconductor pattern has a second length, and wherein the first length is greater than the second length.

公开(公告)号：US20230261079A1

公开(公告)日：2023-08-17

申请号：US17987126

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun SONG ,  Pilkwang KIM ,  Joohyung YOU ,  Sungmin KIM ,  Yonghee PARK ,  Young-Seok SONG ,  Takeshi OKAGAKI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0847 ,  H01L29/6656

Abstract: Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first and second regions, a device isolation pattern in the substrate, a lower separation dielectric pattern on the first region of the substrate, first channel patterns on the lower separation dielectric pattern, a first gate electrode on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.

公开(公告)号：US20220157853A1

公开(公告)日：2022-05-19

申请号：US17369236

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.