-
公开(公告)号:US20210294365A1
公开(公告)日:2021-09-23
申请号:US17069500
申请日:2020-10-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SUNGMIN YOO , Joowon Park , Tae-Hwang Kong , Sangho Kim , Hyunmyoung Kim , Jaeseung Lee
IPC: G05F1/46 , G05F1/565 , G06F1/3206 , G05F3/16
Abstract: A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.
-
公开(公告)号:US10685977B2
公开(公告)日:2020-06-16
申请号:US16231710
申请日:2018-12-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jongwon Kim , Hyeong Park , Hyunmin Lee , Hojong Kang , Joowon Park , Seungmin Song
IPC: H01L27/11582 , H01L27/11565 , H01L27/11575
Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.
-
公开(公告)号:US10608091B2
公开(公告)日:2020-03-31
申请号:US16121020
申请日:2018-09-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Tae-Wan Lim , Hojong Kang , Joowon Park
IPC: H01L23/52 , H01L29/423 , H01L23/31 , H01L27/11582 , H01L21/28 , H01L23/485 , H01L23/522 , H01L27/1157 , H01L27/11575 , H01L21/768 , H01L29/66 , H01L29/792
Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.
-
公开(公告)号:US12219763B2
公开(公告)日:2025-02-04
申请号:US17744092
申请日:2022-05-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jisung Cheon , Byunggon Park , Joowon Park , Sangjun Hong , Jinsoo Lim
IPC: H10B43/27 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/535 , H10B41/27 , H10B41/35 , H10B43/35
Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.
-
公开(公告)号:US10186519B2
公开(公告)日:2019-01-22
申请号:US15059993
申请日:2016-03-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jongwon Kim , Hyeong Park , Hyunmin Lee , Hojong Kang , Joowon Park , Seungmin Song
IPC: H01L27/11582 , H01L27/11565 , H01L27/11575
Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.
-
公开(公告)号:US20190019872A1
公开(公告)日:2019-01-17
申请号:US16121020
申请日:2018-09-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Tae-Wan LIM , Hojong Kang , Joowon Park
IPC: H01L29/423 , H01L21/28 , H01L23/522 , H01L27/1157 , H01L27/11575 , H01L21/768 , H01L29/66 , H01L29/792 , H01L23/31 , H01L27/11582 , H01L23/485
Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.
-
公开(公告)号:US20220328522A1
公开(公告)日:2022-10-13
申请号:US17854356
申请日:2022-06-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joowon Park , Woongseop Lee , Eiwhan Jung , Jisung Cheon
IPC: H01L27/11582 , H01L27/11526 , H01L27/11556 , H01L23/528 , H01L27/11573 , H01L27/11519 , H01L27/11548 , H01L27/11565 , H01L27/11575 , H01L23/522
Abstract: A semiconductor device includes a peripheral circuit region on a first substrate and including circuit devices, a memory cell region on a second substrate overlaid on the first substrate, with the memory cell region including gate electrodes stacked to be spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and channel structures which extend vertically on the second substrate and penetrate through the gate electrodes. The channel structures may include a channel layer. The semiconductor device includes a through-wiring region with through-contact plugs that extend in the first direction and that electrically connect the memory cell region and the peripheral circuit region to each other, with the through-wiring region including an insulating region that surrounds the through-contact plugs. The through-wiring region further includes dummy channel structures regularly arranged throughout the through-wiring region and which include the channel layer.
-
公开(公告)号:US11335695B2
公开(公告)日:2022-05-17
申请号:US16710402
申请日:2019-12-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jisung Cheon , Byunggon Park , Joowon Park , Sangjun Hong , Jinsoo Lim
IPC: H01L27/11578 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L23/522 , H01L23/528 , H01L21/768 , H01L21/28 , H01L23/535
Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.
-
公开(公告)号:US10861864B2
公开(公告)日:2020-12-08
申请号:US16682133
申请日:2019-11-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Da Woon Jeong , Jihye Kim , Joowon Park
IPC: H01L27/11565 , H01L27/11582 , H01L27/11575 , H01L27/1157
Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.
-
公开(公告)号:US11543841B2
公开(公告)日:2023-01-03
申请号:US17069500
申请日:2020-10-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sungmin Yoo , Joowon Park , Tae-Hwang Kong , Sangho Kim , Hyunmyoung Kim , Jaeseung Lee
IPC: G05F1/46 , G05F3/16 , G06F1/3206 , G05F1/565
Abstract: A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.
-
-
-
-
-
-
-
-
-