公开(公告)号：US20240055421A1

公开(公告)日：2024-02-15

申请号：US18320013

申请日：2023-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Yun KWEON ,  Yeong Beom KO ,  Woo Ju KIM ,  Jung Seok RYU ,  Hwa Young LEE ,  Hyun Su HWANG

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L25/0652 ,  H01L24/08 ,  H01L23/5386 ,  H01L23/5384 ,  H01L23/3121 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/181 ,  H01L2224/081 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A method for manufacturing semiconductor device includes preparing a semiconductor wafer including a first semiconductor substrate and a first through silicon via; removing a trim region of the first semiconductor substrate along an edge portion of the semiconductor wafer to form a remaining edge region; attaching the semiconductor wafer to a carrier substrate, wherein the remaining edge region is in contact with the carrier substrate; forming an edge protection layer along the remaining edge region; exposing the first through silicon via by removing a predetermined depth of the first semiconductor substrate; forming a second final passivation layer to expose the upper surface of the first through silicon via; forming a plurality of first upper connection pads on the second final passivation layer; and dicing the semiconductor wafer into a plurality of first semiconductor chips.

公开(公告)号：US20230021152A1

公开(公告)日：2023-01-19

申请号：US17665652

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Su HWANG ,  Jun Yun KWEON ,  Jum Yong PARK ,  Sol Ji SONG ,  Dong Joon OH ,  Chung Sun LEE

IPC: H01L23/00

Abstract: A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.