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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11600620B2

    公开(公告)日：2023-03-07

    申请号：US17353398

    申请日：2021-06-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Il Han ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

    Semiconductor device and method of manufacturing the semiconductor device
    3.
    发明授权
    Semiconductor device and method of manufacturing the semiconductor device 有权

    公开(公告)号：US11239311B2

    公开(公告)日：2022-02-01

    申请号：US16897492

    申请日：2020-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hui-Jung Kim ,  Kyu Jin Kim ,  Sang-Il Han ,  Kyu Hyun Lee ,  Woo Young Choi ,  Yoo Sang Hwang

    IPC: H01L29/06 ,  H01L29/423

    Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210313329A1

    公开(公告)日：2021-10-07

    申请号：US17353398

    申请日：2021-06-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Il Han ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09318570B2

    公开(公告)日：2016-04-19

    申请号：US14472571

    申请日：2014-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Il Han ,  Jong-Un Kim ,  Jun-Soo Kim

    IPC: H01L27/00 ,  H01L29/00 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108

    CPC classification number: H01L29/4236 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7827

    Abstract: Provided is a semiconductor device, including a substrate including a device isolation layer and an active region isolated by the device isolation layer; a trench in the active region; a gate electrode filling at least a portion of the trench; a recess in the substrate at one side of the gate electrode, the recess overlapping a portion of the device isolation layer and the active region; and a lower contact plug filling the recess.

    Abstract translation: 提供一种半导体器件，包括：衬底，其包括器件隔离层和由器件隔离层隔离的有源区; 活跃区域的沟槽; 填充所述沟槽的至少一部分的栅电极; 在栅电极的一侧的衬底中的凹部，凹部与器件隔离层的一部分和有源区重叠; 以及填充凹部的下接触塞。

    Semiconductor memory device and method of fabricating the same
    7.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09472445B2

    公开(公告)日：2016-10-18

    申请号：US14472765

    申请日：2014-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Il Han ,  Jong-Un Kim

    IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/108

    CPC classification number: H01L21/762 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0649

    Abstract: A semiconductor memory device including a substrate, a first element isolation film pattern, and a second element isolation film pattern. The substrate includes a first region and a second region. The first element isolation film pattern is in the first region and corresponds to a first active region. The second element isolation film pattern is in the second region and corresponds to a second active region. The first element isolation film pattern includes a first material and the second element isolation film pattern includes a second material different from the first material.

    Abstract translation: 一种半导体存储器件，包括衬底，第一元件隔离膜图案和第二元件隔离膜图案。 衬底包括第一区域和第二区域。 第一元件隔离膜图案位于第一区域中并且对应于第一有源区域。 第二元件隔离膜图案在第二区域中并且对应于第二有源区域。 第一元件隔离膜图案包括第一材料，第二元件隔离膜图案包括与第一材料不同的第二材料。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11715760B2

    公开(公告)日：2023-08-01

    申请号：US17587444

    申请日：2022-01-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hui-Jung Kim ,  Kyu Jin Kim ,  Sang-Il Han ,  Kyu Hyun Lee ,  Woo Young Choi ,  Yoo Sang Hwang

    IPC: H01L29/06 ,  H01L29/423

    CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/42368

    Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

    Semiconductor device and method of fabricating the same
    10.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11270933B2

    公开(公告)日：2022-03-08

    申请号：US17038085

    申请日：2020-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Il Han ,  Sunghee Han

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00

    Abstract: A semiconductor device comprises a substrate including a cell array region and a peripheral circuit region that surrounds the cell array region. The cell array region includes landing pads disposed on the substrate and first bottom electrodes disposed on and connected to corresponding landing pads. The peripheral circuit region includes conductive lines disposed on the substrate, a first conductive pad disposed on and spaced apart from the conductive lines, a dielectric pattern disposed between the conductive lines and the first conductive pad, and a plurality of second bottom electrodes disposed on and connected in common to the first conductive pad. A height of each of the first bottom electrodes is greater than a height of each of the second bottom electrodes. Top surfaces of the first bottom electrodes are located at a same level as a level of top surfaces of the second bottom electrodes.

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