公开(公告)号：US20240363526A1

公开(公告)日：2024-10-31

申请号：US18421431

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuhoon CHOI ,  Seungseok HA ,  Seowoo NAM

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H10B12/00 ,  H10B41/30 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/544 ,  H10B12/09 ,  H10B12/50 ,  H10B41/30 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40 ,  H01L2223/54426

Abstract: A semiconductor device according to some example embodiments may include: a substrate having a first region and a second region; a lower interlayer insulating layer on the first region and the second region of the substrate; an upper interlayer insulating layer on the lower interlayer insulating layer; a via structure penetrating through the upper interlayer insulating layer in the first region; a plurality of metal wirings extending in a first direction on the via structure and electrically connected to the via structure; trenches on a same level as that of the via structure and in the upper interlayer insulating layer, in the second region; and a dummy wiring layer having a curved structure along upper surfaces of the trenches, the upper interlayer insulating layer, and the lower interlayer insulating layer.

公开(公告)号：US20240063018A1

公开(公告)日：2024-02-22

申请号：US18366470

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seowoo NAM ,  Kyungsoo KIM

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877

Abstract: A method of fabricating a semiconductor device, includes forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming mandrel lines on the hard mask layer, each of the mandrel lines extending in a first direction; forming spacers on both sidewalls of each of mandrel lines; removing the plurality of mandrel lines from the spacers; forming a first linear opening corresponding to a first region of a space between adjacent ones of the spacers, in the hard mask layer; forming a second linear opening corresponding to a second region of the space between the adjacent ones, the second linear opening being adjacent to the first linear opening in the first direction; forming trenches in the dielectric layer using the hard mask layer; and interconnection lines by filling the trenches with a conductive material.

公开(公告)号：US20250096133A1

公开(公告)日：2025-03-20

申请号：US18645765

申请日：2024-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seowoo NAM ,  Heonjong SHIN ,  Juneyoung PARK ,  Sanghee LEE

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a fin-type active region extending in a first horizontal direction on a substrate, a plurality of nanosheets facing a fin top of the fin-type active region, a gate line on the fin-type active region, the gate line surrounding each of the nanosheets and extending in a second horizontal direction, and a source/drain region on the fin-type active region. The gate line includes a main gate portion on the nanosheet stack, a first sub gate portion, a second sub gate portion, and a third sub gate portion. A width of the first sub gate portion in the first horizontal direction is greater than or equal to a width of the third sub gate portion in the first horizontal direction and the width of the first sub gate portion is less than a width of the second sub gate portion in the first horizontal direction.