公开(公告)号：US11196151B2

公开(公告)日：2021-12-07

申请号：US16632693

申请日：2018-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Ho Ahn ,  Sang Il Park ,  Bo Ram Namgoong ,  Jae Bong Chun

IPC: H01Q1/28 ,  H01Q5/30 ,  H01Q1/24 ,  H01Q1/48 ,  H01Q13/10

Abstract: An electronic device according to an embodiment of the present invention comprises a first conductive plate; and a second conductive plate which extends from the first conductive plate at a first angle to the first conductive plate, wherein the first conductive plate and the second conductive plate comprise a conductive member which forms a cavity opened in a first direction perpendicular to the first conductive plate; a first radiation unit which is disposed apart from the first conductive plate by a first distance in a first direction; a second radiation unit which is disposed apart from the first conductive plate by a second distance in a second direction opposite to the first direction; at least one wireless communication circuit which feeds electricity to the first radiation unit and the second radiation unit; and a processor which is electrically connected with the wireless communication circuit, the processor can be set to cause the wireless communication circuit to receive a signal of a first frequency having a directivity in the first direction on the basis of the cavity formed by the first radiation unit and the conductive member, and to receive a second frequency signal on the basis of the coupling of the second radiation unit and at least a portion of the conductive member. In addition, various embodiments understood from the specification may be possible.

公开(公告)号：US10416896B2

公开(公告)日：2019-09-17

申请号：US15603255

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Il O ,  Nam Sung Kim ,  Young-Hoon Son ,  Chan-Kyung Kim ,  Ho-Young Song ,  Jung Ho Ahn ,  Sang-Joon Hwang

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US11544213B2

公开(公告)日：2023-01-03

申请号：US17369298

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

Inventor： Dongyoung Kim ,  Jung Ho Ahn ,  Sunjung Lee ,  Jaewan Choi

IPC: G06F15/80 ,  G06F9/30 ,  G06N3/063

Abstract: A neural processor is provided. The neural processor includes a matrix device which is configured to generate an output feature map by processing a standard convolution operation and which has a systolic array architecture, and accelerators with an adder-tree structure which are configured to process depth-wise convolution operations for each of elements of the output feature map corresponding to lanes of the matrix device.

公开(公告)号：US11169711B2

公开(公告)日：2021-11-09

申请号：US16524749

申请日：2019-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Il O ,  Nam Sung Kim ,  Young-Hoon Son ,  Chan-Kyung Kim ,  Ho-Young Song ,  Jung Ho Ahn ,  Sang-Joon Hwang

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US11436168B2

公开(公告)日：2022-09-06

申请号：US17192032

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

Inventor： Seung Wook Lee ,  Hweesoo Kim ,  Jung Ho Ahn

IPC: G06F13/16 ,  G06F15/80

Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.

公开(公告)号：US09767887B2

公开(公告)日：2017-09-19

申请号：US14734101

申请日：2015-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Young Hoon Son ,  Jung Ho Ahn ,  Seong Il O

IPC: G11C11/4094 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4076

CPC classification number: G11C11/4094 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1063 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.

公开(公告)号：US11966344B2

公开(公告)日：2024-04-23

申请号：US17876116

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

Inventor： Seung Wook Lee ,  Hweesoo Kim ,  Jung Ho Ahn

IPC: G06F13/16 ,  G06F15/80

CPC classification number: G06F13/1668 ,  G06F15/8038

Abstract: An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.