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1.发明申请公开(公告)号：US20180322008A1
公开(公告)日：2018-11-08
申请号：US16015534
申请日：2018-06-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C29/52 , G11C29/70 , G11C2029/0409 , G11C2029/0411
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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公开(公告)号：US10037244B2
公开(公告)日：2018-07-31
申请号：US15238216
申请日：2016-08-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C29/52 , G11C29/70 , G11C2029/0409 , G11C2029/0411
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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公开(公告)号：US09972377B2
公开(公告)日：2018-05-15
申请号：US15262183
申请日：2016-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Min Oh , Ho-Young Song
IPC: G11C11/406 , G11C11/408 , G11C11/4076
CPC classification number: G11C11/40615 , G11C11/406
Abstract: A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.
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4.发明申请MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE 有权存储器件，其操作方法和具有存储器件的电子器件公开(公告)号：US20130322149A1
公开(公告)日：2013-12-05
申请号：US13771633
申请日：2013-02-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Je-Min Ryu , Gil-Su Kim , Jong-Min Oh , Sung-Min Seo , Ho-Young Song , Yong-Ho Cho
CPC classification number: G11C17/16 , G11C7/1045 , G11C17/18 , G11C29/802
Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.
Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。
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公开(公告)号：US11994948B2
公开(公告)日：2024-05-28
申请号：US18164349
申请日：2023-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C29/70
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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Patent Agency Ranking
公开(公告)号：US10705908B2
公开(公告)日：2020-07-07
申请号：US16015534
申请日：2018-06-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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公开(公告)号：US10699991B2
公开(公告)日：2020-06-30
申请号：US15841937
申请日：2017-12-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi-Goo Kang , Sun-Woo Kim , Jong-Sup Song , Ho-Young Song
Abstract: A packaged light emitting device can include a mounting substrate including first and second electrode portions that are separated by a recess defined by a first side surface of the first electrode portion and a second side surface of the second electrode portion that is opposite the first side surface. An insulation support member can partially fill a lower portion of the recess to partially cover the first side surface and partially cover the second side surface. A light emitting device can be coupled to the first and second electrode portions of the mounting substrate and a sealing member can be on the mounting substrate covering the light emitting device.
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公开(公告)号：US09941247B2
公开(公告)日：2018-04-10
申请号：US14790451
申请日：2015-07-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hae-Suk Lee , Kyo-Min Sohn , Ho-Young Song , Sang-Hoon Shin , Han-Vit Jung
IPC: G11C11/4093 , H01L25/065 , G11C7/10
CPC classification number: H01L25/0657 , G11C7/1066 , G11C7/1069 , H01L2924/0002 , H01L2924/00
Abstract: A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N−1).
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公开(公告)号：US20170229192A1
公开(公告)日：2017-08-10
申请号：US15498855
申请日：2017-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyo-Min Sohn , Ho-Young Song , Sang-Joon Hwang , Cheol Kim , Dong-Hyun Sohn
IPC: G11C29/44 , G11C29/42 , G11C11/4094 , G11C29/00 , G11C11/4078 , G11C17/16 , G11C17/18 , G11C29/36 , G11C11/4096
CPC classification number: G11C29/4401 , G01R31/3187 , G06F11/2053 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C8/06 , G11C8/10 , G11C11/40 , G11C11/4078 , G11C11/4094 , G11C11/4096 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/36 , G11C29/42 , G11C29/44 , G11C29/56 , G11C29/56008 , G11C29/78 , G11C29/785 , G11C2029/4402 , G11C2029/5606
Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
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公开(公告)号：US09384861B2
公开(公告)日：2016-07-05
申请号：US14623133
申请日：2015-02-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Min Oh , Ho-Young Song , Seong-Jin Jang
CPC classification number: G11C29/86 , G11C7/1036 , G11C7/1051 , G11C8/04 , G11C11/4093 , G11C16/20 , G11C17/16 , G11C2029/0407 , G11C2207/107
Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.
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