利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.061 秒)

    Neuromorphic circuit having 3D stacked structure and semiconductor device having the same
    1.
    发明授权
    Neuromorphic circuit having 3D stacked structure and semiconductor device having the same 有权

    公开(公告)号：US11410026B2

    公开(公告)日：2022-08-09

    申请号：US16191906

    申请日：2018-11-15

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Woo-Yeong Cho ,  Seong-Il O ,  Hak-Soo Yu ,  Min-Su Choi

    IPC分类号： G06N3/063 ,  G06N3/04 ,  H01L27/24 ,  H01L25/065 ,  G06F15/163

    摘要： Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20180122442A1

    公开(公告)日：2018-05-03

    申请号：US15691985

    申请日：2017-08-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： JONG-PIL SON ,  Seong-Il O

    IPC分类号： G11C8/08 ,  G11C7/06 ,  G11C7/12

    CPC分类号： G11C8/08 ,  G11C7/065 ,  G11C7/12 ,  G11C8/18

    摘要： A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device.

    Word-line timing control in a semiconductor memory device and a memory system including the same
    4.
    发明授权
    Word-line timing control in a semiconductor memory device and a memory system including the same 有权

    公开(公告)号：US10482938B2

    公开(公告)日：2019-11-19

    申请号：US15691985

    申请日：2017-08-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jong-Pil Son ,  Seong-Il O

    IPC分类号： G11C8/08 ,  G11C7/06 ,  G11C7/12 ,  G11C8/18

    摘要： A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device.

    METHOD OF PERFORMING INTERNAL PROCESSING OPERATION OF MEMORY DEVICE
    5.
    发明申请
    METHOD OF PERFORMING INTERNAL PROCESSING OPERATION OF MEMORY DEVICE 有权

    公开(公告)号：US20220383938A1

    公开(公告)日：2022-12-01

    申请号：US17883498

    申请日：2022-08-08

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Pavan Kumar KASIBHATLA ,  Seong-Il O ,  Hak-soo Yu

    IPC分类号： G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

    摘要： Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

    Semiconductor memory device and memory module including the same
    6.
    发明授权
    Semiconductor memory device and memory module including the same 有权

    公开(公告)号：US11056173B2

    公开(公告)日：2021-07-06

    申请号：US16138086

    申请日：2018-09-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seong-Il O

    IPC分类号： G11C11/408 ,  G06F21/72 ,  G11C7/10 ,  G06F3/06 ,  G06F21/60 ,  H04L9/08

    摘要： A semiconductor memory device includes a memory core including a plurality of memory cells, an on-chip processor and a memory security controller. The on-chip processor performs on-chip data processing. The memory security controller decrypts encrypted data provided from the memory core or from a memory controller and to provide the decrypted data to the on-chip processor and encrypts result data from the on-chip processor to provide result-encrypted data to the memory core or the memory controller. Data processing efficiency may be enhanced without degradation of data security by decrypting the encrypted data in the semiconductor memory device to perform the on-chip data processing.

    MEMORY MODULE, MEMORY DEVICE, AND PROCESSING DEVICE HAVING A PROCESSOR MODE, AND MEMORY SYSTEM
    7.
    发明申请
    MEMORY MODULE, MEMORY DEVICE, AND PROCESSING DEVICE HAVING A PROCESSOR MODE, AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20190354292A1

    公开(公告)日：2019-11-21

    申请号：US16524749

    申请日：2019-07-29

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seong-Il O ,  Nam Sung KIM ,  Young-Hoon SON ,  Chan-Kyung KIM ,  Ho-Young SONG ,  Jung Ho AHN ,  Sang-Joon HWANG

    IPC分类号： G06F3/06 ,  G06F13/16

    摘要： A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.