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    Resistive memory device, memory system including the same and method of reading data from the same
    1.
    发明授权
    Resistive memory device, memory system including the same and method of reading data from the same 有权
    电阻式存储器件，包括相同的存储器系统和从其读取数据的方法

    公开(公告)号：US09368178B2

    公开(公告)日：2016-06-14

    申请号：US14722031

    申请日：2015-05-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan-Kyung Kim

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659

    Abstract: A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively.

    Abstract translation: 电阻式存储器件可以包括第一和第二电阻存储器单元，参考电流发生器以及第一和第二位线读出放大器。 参考电流发生器可以被配置为将第一和第二参考电流施加到第一公共节点。 提供给第一公共节点的第一参考电流和第二参考电流的总参考电流可以被第一公共节点划分为第一感测电流和第二感测电流。 第一和第二感测电流可以分别由第一公共节点提供给第一和第二位线读出放大器。 第一和第二位线读出放大器可以被配置为分别基于第一和第二感测电流来感测第一电阻存储器单元的第一数据和第二电阻存储器单元的第二数据。

    Method of reconfiguring DQ pads of memory device and DQ pad reconfigurable memory device
    3.
    发明授权
    Method of reconfiguring DQ pads of memory device and DQ pad reconfigurable memory device 有权

    公开(公告)号：US10372658B2

    公开(公告)日：2019-08-06

    申请号：US15677475

    申请日：2017-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan-Kyung Kim

    IPC: G11C8/00 ,  G06F13/40 ,  G06F3/00 ,  G06F13/12

    Abstract: A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the M3 and M4 metal layers of the memory device.

    Memory device supporting skip calculation mode and method of operating the same
    6.
    发明授权
    Memory device supporting skip calculation mode and method of operating the same 有权

    公开(公告)号：US11194579B2

    公开(公告)日：2021-12-07

    申请号：US16199679

    申请日：2018-11-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Sung Shin ,  Sung-Ho Park ,  Chan-Kyung Kim ,  Yong-Sik Park ,  Sang-Hoon Shin

    IPC: G06F9/355 ,  G06F9/30 ,  G06F9/345 ,  G06F12/0815

    Abstract: A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.

    Common source semiconductor memory device
    8.
    发明授权
    Common source semiconductor memory device 有权
    普通源半导体存储器件

    公开(公告)号：US09076539B2

    公开(公告)日：2015-07-07

    申请号：US14105782

    申请日：2013-12-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan-Kyung Kim ,  Dong-Min Kim ,  Hong-Sun Hwang

    IPC: G11C11/16

    CPC classification number: G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1697

    Abstract: A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.

    Abstract translation: 存储器件包括单元阵列和公共源极线补偿电路。 单元阵列包括分别连接在多个位线和一个公共源极线之间的多个正常单元单元。 公共源极线补偿电路向公共源极线提供多个补偿写入电流，以补偿通过正常单元单元同时输入到共用源极线或从共模源极线输出的多个写入电流。

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