公开(公告)号：US20220190134A1

公开(公告)日：2022-06-16

申请号：US17460446

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEO JIN JEONG ,  Do Hyun GO ,  Seok Hoon KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Moon Seung YANG ,  Min-Hee CHOI ,  Ryong HA

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US20220181498A1

公开(公告)日：2022-06-09

申请号：US17391342

申请日：2021-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek KIM ,  Seok Hoon KIM ,  Ryong HA ,  Pan Kwi PARK ,  Dong Suk SHIN

IPC: H01L29/786 ,  H01L29/66

Abstract: There is provided a semiconductor device comprising an active pattern, including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction, a plurality of gate structures on the lower pattern to be spaced apart from each other in the first direction and including a gate electrode and a gate insulating film wrapping the plurality of sheet patterns, a source/drain recess defined between the gate structures adjacent to each other, and a source/drain pattern inside the source/drain recess and including a semiconductor blocking film formed continuously along the source/drain recess, wherein the source/drain recesses include a plurality of width extension regions, and a width of each of the width extension regions in the first direction increases and then decreases, as it goes away from an upper surface of the lower pattern.

公开(公告)号：US20230056095A1

公开(公告)日：2023-02-23

申请号：US17734564

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu CHO ,  Sang Gil LEE ,  Seok Hoon KIM ,  Yong Seung KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Si Hyung LEE ,  Yang XU

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first active pattern on the first region, a first gate structure having a first width in the first direction, on the first active pattern, a first epitaxial pattern disposed in the first active pattern on a side surface of the first gate structure, a second active pattern on the second region, a second gate structure having a second width greater than the first width in the first direction, on the second active pattern and a second epitaxial pattern disposed in the second active pattern on a side surface of the second gate structure. Each of the first epitaxial pattern and the second epitaxial pattern includes silicon germanium (SiGe), and a first Ge concentration of the first epitaxial pattern is lower than a second Ge concentration of the second epitaxial pattern.

公开(公告)号：US20210408300A1

公开(公告)日：2021-12-30

申请号：US17470341

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Seung YANG ,  Eun Hye CHOI ,  Seung Mo KANG ,  Yong Seung KIM ,  Jung Taek KIM ,  Min-Hee CHOI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.

公开(公告)号：US20240297234A1

公开(公告)日：2024-09-05

申请号：US18661171

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Jin JEONG ,  Do Hyun GO ,  Seok Hoon KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Moon Seung YANG ,  Min-Hee CHOI ,  Ryong HA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US20240194786A1

公开(公告)日：2024-06-13

申请号：US18531898

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Suk SHIN ,  Jung Taek KIM ,  Hyun-Kwan YU ,  Seok Hoon KIM ,  Pan Kwi PARK ,  Seo Jin JEONG ,  Nam Kyu CHO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66545

Abstract: There is provided a semiconductor device capable of improving performance and reliability of an element. The semiconductor device includes an active pattern extending in a first direction, and a plurality of gate structures spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode extending in a second direction and a gate spacer on a sidewall of the gate electrode and a source/drain pattern disposed between adjacent gate structures. The gate structure comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion protruding in a third direction beyond an upper surface of the active pattern. A maximum width of the upper portion of the semiconductor filling layer in the first direction is greater than a width of the semiconductor filling layer in the first direction on the upper surface of the active pattern. The semiconductor liner layer comprises an outer surface in contact with the active pattern and an inner surface facing the semiconductor filling layer. In a plan view, the inner surface of the semiconductor liner layer comprises a concave region.

公开(公告)号：US20240021675A1

公开(公告)日：2024-01-18

申请号：US18125411

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Kyu CHO ,  Seok Hoon KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Seo Jin JEONG

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes: first and second channel structures spaced apart from each other in a first direction; and a source/drain pattern, between the first and second channel structures, including a first interface contacting the first channel structure and a second interface contacting the second channel structure, wherein, in a plan view, the source/drain pattern includes first and second side walls opposite to each other in a second direction, the first side wall includes a first sloped side wall, a second sloped side wall, and a first horizontal intersection at which the first and second sloped side walls meet, a width of the first interface is different from a width of the second interface, in the second direction, and a distance from the first interface to the first horizontal intersection is greater than a distance from the second interface to the first horizontal intersection, in the first direction.