公开(公告)号：US20190148632A1

公开(公告)日：2019-05-16

申请号：US16122056

申请日：2018-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Min LEE ,  Ju-Hyun KIM ,  Jung-Hwan PARK ,  Se-Chung OH ,  Dong-Kyu LEE ,  Kyung-Il HONG

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22

Abstract: In a method of manufacturing a variable resistance memory device, an MTJ structure layer is formed on a substrate. The MTJ structure layer is etched in an etching chamber to form an MTJ structure. The substrate having the MTJ structure thereon is transferred to a deposition chamber through a transfer chamber. A protection layer covering a sidewall of the MTJ structure is formed in the deposition chamber. The etching chamber, the transfer chamber, and the deposition chamber are kept in a high vacuum state equal to or more than about 10−8 Torr.

公开(公告)号：US20190097124A1

公开(公告)日：2019-03-28

申请号：US16101243

申请日：2018-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Myoung LEE ,  Ju-Hyun KIM ,  Jung-Hwan PARK ,  Se-Chung OH ,  Young-Man JANG

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: An MRAM device includes a lower electrode, a blocking pattern on the lower electrode and including a binary metal boride in an amorphous state, a seed pattern on the blocking pattern and including a metal, an MTJ structure on the seed pattern, and an upper electrode on the MTJ structure.

公开(公告)号：US20180277750A1

公开(公告)日：2018-09-27

申请号：US15996605

申请日：2018-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Uk KIM ,  Jung-Moo LEE ,  Soon-Oh PARK ,  Jung-Hwan PARK ,  Sug-Woo JUNG

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.