公开(公告)号：US20150357339A1

公开(公告)日：2015-12-10

申请号：US14826814

申请日：2015-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil SHIM ,  Jang-Gn YUN ,  Jeonghyuk CHOI ,  Kwang Soo SEOL ,  Jaehoon JANG ,  Jungdal CHOI

IPC: H01L27/115 ,  H01L23/535

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

Abstract translation: 提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和 第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到 第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

公开(公告)号：US20140367764A1

公开(公告)日：2014-12-18

申请号：US14472952

申请日：2014-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegoo LEE ,  Youngwoo PARK ,  Jungdal CHOI

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

Abstract: A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

Abstract translation: 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

公开(公告)号：US20140269103A1

公开(公告)日：2014-09-18

申请号：US14291099

申请日：2014-05-30

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Sung-il CHANG ,  Changseok KANG ,  Jungdal CHOI

IPC: H01L29/66 ,  G11C16/14 ,  G11C16/10

CPC classification number: H01L29/66833 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/513 ,  H01L29/792 ,  H01L29/7926

Abstract: A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly, the reliability of the nonvolatile memory device is improved.

Abstract translation: 提供一种非易失性存储器件及其制造方法。 在非易失性存储器件中，在阱绝缘层和栅电极之间设置阻挡绝缘层。 在隔离绝缘层中设置有与栅电极间隔开的固定电荷层。 因此，提高了非易失性存储装置的可靠性。

公开(公告)号：US20130100742A1

公开(公告)日：2013-04-25

申请号：US13653798

申请日：2012-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun LEE ,  Yoocheol SHIN ,  Jungdal CHOI

IPC: G11C11/34

CPC classification number: G11C11/34 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: A nonvolatile memory device is provided. The device may include a plurality of cell strings that are configured to share a bit line, word lines, and selection lines. Each of the cell strings may include a plurality of memory cells connected in series to each other and a string selection device controlling connections between the memory cells and the bit line, and the string selection device may include a first string selection element with a first threshold voltage and a second string selection element connected in series to the first string selection element and having a second threshold voltage different from the first threshold voltage. At least one of the first and second string selection elements may include a plurality of switching elements connected in series to each other.

Abstract translation: 提供非易失性存储器件。 该设备可以包括被配置为共享位线，字线和选择线的多个单元串。 每个单元串可以包括彼此串联连接的多个存储器单元和用于控制存储器单元和位线之间的连接的串选择设备，并且串选择设备可以包括具有第一阈值的第一串选择单元 电压和第二串选择元件串联连接到第一串选择元件并且具有不同于第一阈值电压的第二阈值电压。 第一和第二串选择元件中的至少一个可以包括彼此串联连接的多个开关元件。