公开(公告)号：US09799823B1

公开(公告)日：2017-10-24

申请号：US15094059

申请日：2016-04-08

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd.

Inventor： Guohan Hu ,  Kwangseok Kim ,  Younghyun Kim ,  Junghyuk Lee ,  Luqiao Liu ,  Jeong-Heon Park

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01L43/08 ,  H01L43/10

Abstract: Techniques relate to forming a magnetic tunnel junction (MTJ). A magnetic reference layer is formed adjacent to a tunnel barrier layer. The magnetic reference layer includes a pinned layer, a spacer layer adjacent to the pinned layer, and a polarizing enhancement layer adjacent to the spacer layer. A magnetic free layer is formed adjacent to the tunnel barrier layer so as to be opposite the magnetic reference layer.

公开(公告)号：US20220028928A1

公开(公告)日：2022-01-27

申请号：US17380081

申请日：2021-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung Seo ,  Kangho Lee ,  Yoonjong Song ,  Junghyuk Lee

IPC: H01L27/22 ,  H01L27/112

Abstract: A magnetic memory device includes a plurality of first bit lines and a plurality of second bit lines, a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines, a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first region, the plurality of first memory cells respectively including a first memory device and a first selection transistor, and a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second region, the plurality of second memory cells respectively including a second memory device and a second selection transistor.

公开(公告)号：US09893273B2

公开(公告)日：2018-02-13

申请号：US15094052

申请日：2016-04-08

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd.

Inventor： Guohan Hu ,  Junghyuk Lee ,  Jeong-Heon Park

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques relate to forming a semiconductor device. A magnetic pinned layer is formed adjacent to a tunnel barrier layer. A magnetic free layer is formed adjacent to the tunnel barrier layer, such that the tunnel barrier layer is sandwiched between the magnetic pinned layer and the magnetic free layer. The magnetic free layer includes a first magnetic layer, a second magnetic layer disposed on top of the first magnetic layer, and a third magnetic layer disposed on top of the second magnetic layer. The second magnetic layer of the magnetic free layer includes an additional material, and the additional material is a selection of at least one of Be, Mg, Al, Ca, B, C, Si, V, Cr, Ti, and Mn.

公开(公告)号：US12035540B2

公开(公告)日：2024-07-09

申请号：US17380081

申请日：2021-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung Seo ,  Kangho Lee ,  Yoonjong Song ,  Junghyuk Lee

IPC: H10B61/00 ,  H10B20/20

CPC classification number: H10B61/22 ,  H10B20/20

Abstract: A magnetic memory device includes a plurality of first bit lines and a plurality of second bit lines, a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines, a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first region, the plurality of first memory cells respectively including a first memory device and a first selection transistor, and a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second region, the plurality of second memory cells respectively including a second memory device and a second selection transistor.

公开(公告)号：US20170294575A1

公开(公告)日：2017-10-12

申请号：US15094052

申请日：2016-04-08

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd.

Inventor： Guohan Hu ,  Junghyuk Lee ,  Jeong-Heon Park

IPC: H01L43/10 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques relate to forming a semiconductor device. A magnetic pinned layer is formed adjacent to a tunnel barrier layer. A magnetic free layer is formed adjacent to the tunnel barrier layer, such that the tunnel barrier layer is sandwiched between the magnetic pinned layer and the magnetic free layer. The magnetic free layer includes a first magnetic layer, a second magnetic layer disposed on top of the first magnetic layer, and a third magnetic layer disposed on top of the second magnetic layer. The second magnetic layer of the magnetic free layer includes an additional material, and the additional material is a selection of at least one of Be, Mg, Al, Ca, B, C, Si, V, Cr, Ti, and Mn.