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公开(公告)号：US20200021278A1
公开(公告)日：2020-01-16
申请号：US16270622
申请日：2019-02-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kang-yeop Choo , Woo-seok Kim , Tae-ik Kim
Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof. A negative feedback circuit is provided, which has first and second current carrying terminals electrically coupled to the first output terminal of the current mirror and the first node of the variable resistance circuit, respectively, and a control terminal electrically coupled to the input node of the oscillation circuit.
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公开(公告)号：US09989588B2
公开(公告)日：2018-06-05
申请号：US15432731
申请日：2017-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kang-yeop Choo , Hyun-ik Kim , Tae-ik Kim , Ji-hyun Kim , Woo-seok Kim
IPC: H03L7/06 , G01R31/317 , H03L7/091 , H03L7/183
CPC classification number: G01R31/31709 , H03K5/1565 , H03L7/091 , H03L7/183
Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.
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公开(公告)号：US10812054B2
公开(公告)日：2020-10-20
申请号：US16270622
申请日：2019-02-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kang-yeop Choo , Woo-seok Kim , Tae-ik Kim
Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof. A negative feedback circuit is provided, which has first and second current carrying terminals electrically coupled to the first output terminal of the current mirror and the first node of the variable resistance circuit, respectively, and a control terminal electrically coupled to the input node of the oscillation circuit.
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