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公开(公告)号：US20190280008A1
公开(公告)日：2019-09-12
申请号：US16423680
申请日：2019-05-28
发明人： Ki Jeong Kim , Byoung Jun Choi , O Ik Kwon
IPC分类号： H01L27/11582 , H01L29/792 , H01L23/535 , H01L27/11556 , H01L29/66
摘要： A memory device includes gate electrode layers stacked on top of each other on a substrate, a channel region on a cell region of the substrate and extending through the gate electrode layers in a direction perpendicular to an upper surface of the substrate, cell contacts connected to the gate electrode layers, an active region on a peripheral circuit region of the substrate, planar gate electrode layers on the peripheral circuit region and adjacent to the active region, a cover layer on the active region, and peripheral contacts connected to the active region and the planar gate electrode layers. At least a portion of the peripheral contacts are separated from the cover layer above the planar gate electrode layers.
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公开(公告)号：US09853048B2
公开(公告)日：2017-12-26
申请号：US15226329
申请日：2016-08-02
发明人： Ki Jeong Kim , O Ik Kwon , Jong Kyoung Park , Su Jee Sunwoo
IPC分类号： H01L29/76 , H01L29/788 , H01L27/11582 , H01L27/11565 , H01L21/768 , H01L21/311 , H01L27/11575
CPC分类号： H01L27/11582 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76816 , H01L21/76877 , H01L27/11565 , H01L27/11575
摘要： A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure. The interlayer insulating layer is on the gate electrode layers. The contact plugs are connected to the gate electrode layers through the interlayer insulating layer. The at least one contact insulating layer is within the interlayer insulating layer and surrounds one or more of the contact plugs. The at least one contact insulating layer extends in the first direction.
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