公开(公告)号：US11482522B2

公开(公告)日：2022-10-25

申请号：US16583322

申请日：2019-09-26

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Mun Hyeon Kim ,  Byung Gook Park ,  Keun Hwi Cho ,  Si Hyun Kim ,  Ki Tae Lee

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/306

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure extending in a first direction. The semiconductor device includes an active pattern intersecting the gate structure and having a width in the first direction and a height in a second direction. The width is smaller than the height. Moreover, the semiconductor device includes a source/drain region electrically connected to the active pattern.

公开(公告)号：US10021569B2

公开(公告)日：2018-07-10

申请号：US15257684

申请日：2016-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Seok Joo ,  Yu Jeong Jeon ,  Young Bum Lee ,  Eun Ha Choi ,  Ki Tae Lee ,  Yo Han Lee ,  In Ji Jin

IPC: H04M1/66 ,  H04W12/06 ,  G06F21/36 ,  H04L29/06 ,  H04W12/08 ,  G06F21/32

CPC classification number: H04W12/06 ,  G06F21/32 ,  G06F21/36 ,  G06F2221/2149 ,  H04L63/083 ,  H04L63/0861 ,  H04M1/66 ,  H04W12/08

Abstract: An electronic device and theme applying method thereof are provided. The electronic device includes a user authentication module configured to acquire user authentication information, a display configured to output a page, a memory configured to store at least one theme data applicable to the page, and a processor configured to apply theme data, corresponding to the acquired user authentication information, to the output page.

公开(公告)号：US08705219B2

公开(公告)日：2014-04-22

申请号：US13744424

申请日：2013-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Hee Jeon ,  Doo Hyung Kim ,  Han Gu Kim ,  Woo Jin Seo ,  Ki Tae Lee ,  Hong Wook Lim

IPC: H02H3/22

CPC classification number: H02H9/044 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit includes a first power line; a second power line; a ground line; two stack transistors connected in series between the first power line and the ground line; a first resistor connected between the first power line and a first node; a first transistor and a capacitor connected in series between the first node and the ground line; a second transistor connected between the second power line and a second node; a third transistor connected between the first power line and a third node; an inverter, connected between the third node and the ground line, and having an input connected to the second node; a fourth transistor, connected to the first power line, and having a gate connected to the second node; and a fifth transistor, connected between the second power line and the third node, and having a gate connected to a terminal of the fourth transistor.

Abstract translation: 静电放电（ESD）保护电路包括第一电源线; 第二条电力线 地线 串联连接在第一电源线和地线之间的两个堆叠晶体管; 连接在第一电力线和第一节点之间的第一电阻器; 在第一节点和地线之间串联连接的第一晶体管和电容器; 连接在第二电源线和第二节点之间的第二晶体管; 连接在所述第一电力线和第三节点之间的第三晶体管; 连接在第三节点和接地线之间并具有连接到第二节点的输入的逆变器; 第四晶体管，连接到第一电力线，并且具有连接到第二节点的栅极; 以及第五晶体管，连接在第二电源线和第三节点之间，并且具有连接到第四晶体管的端子的栅极。

公开(公告)号：US10854375B2

公开(公告)日：2020-12-01

申请号：US15805601

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Su Song ,  Ji Won Kim ,  Se Ho Park ,  Ki Tae Lee ,  Chang Ho Lee ,  Chi Hyun Cho

IPC: H02J7/00 ,  H01F27/36 ,  H04B5/00 ,  H01F27/28 ,  H01F38/14 ,  H02J7/02 ,  H01F27/34

Abstract: An electronic device is provided. The electronic device includes a housing and a first coil disposed in the housing and wound around a space formed inside. The housing includes a front cover and a rear cover. The rear cover includes a hole located in a first region of the rear cover that corresponds to the space of the first coil, a first slit that extends from an edge of the rear cover to the hole, and a second slit spaced apart from the first slit and extending from the edge. One end of the second slit is located in a second region of the rear cover that corresponds to the first coil. In addition, various other embodiments recognized through the present specification are possible.

公开(公告)号：US10263752B2

公开(公告)日：2019-04-16

申请号：US15824939

申请日：2017-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Joon Cho ,  Sung Jin Park ,  Dae Ho Kang ,  Chang Won Nam ,  Hyung Yeol Lee ,  Chaiman Lim ,  Ki Tae Lee ,  Sun Min Hwang

IPC: H04W72/04 ,  H04W72/12 ,  H04L27/00 ,  H04L5/00

Abstract: An electronic device includes a first communication module, a second communication module, a memory, a processor configured to be electrically connected with the first communication module and the second communication module, and a memory. The processor is configured to verify a first data packet to be transmitted via the first communication module. The processor is also configured to obtain scheduling information of a second data packet received via the second communication module. The processor is also configured to adjust a time when transmission of the first data packet is started, based on the scheduling information.

公开(公告)号：US20130182359A1

公开(公告)日：2013-07-18

申请号：US13744424

申请日：2013-01-18

Applicant: Samsung Electronics Co., LTD.

Inventor： Chan Hee Jeon ,  Doo Hyung KIM ,  Han Gu Kim ,  Woo Jin Seo ,  Ki Tae Lee ,  Hong Wook Lim

IPC: H02H9/04

CPC classification number: H02H9/044 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit includes a first power line; a second power line; a ground line; two stack transistors connected in series between the first power line and the ground line; a first resistor connected between the first power line and a first node; a first transistor and a capacitor connected in series between the first node and the ground line; a second transistor connected between the second power line and a second node; a third transistor connected between the first power line and a third node; an inverter, connected between the third node and the ground line, and having an input connected to the second node; a fourth transistor, connected to the first power line, and having a gate connected to the second node; and a fifth transistor, connected between the second power line and the third node, and having a gate connected to a terminal of the fourth transistor.

Abstract translation: 静电放电（ESD）保护电路包括第一电源线; 第二条电力线; 地线 串联连接在第一电源线和地线之间的两个堆叠晶体管; 连接在第一电力线和第一节点之间的第一电阻器; 在第一节点和地线之间串联连接的第一晶体管和电容器; 连接在第二电源线和第二节点之间的第二晶体管; 连接在所述第一电力线和第三节点之间的第三晶体管; 连接在第三节点和接地线之间并具有连接到第二节点的输入的逆变器; 第四晶体管，连接到第一电力线，并且具有连接到第二节点的栅极; 以及第五晶体管，连接在第二电源线和第三节点之间，并且具有连接到第四晶体管的端子的栅极。