公开(公告)号：US20200097361A1

公开(公告)日：2020-03-26

申请号：US16575615

申请日：2019-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok SUH ,  Gwan-hyeob KOH ,  Yoon-jong SONG

IPC: G06F11/10 ,  G06F13/40 ,  G06F13/16 ,  G11C7/06

Abstract: A memory system includes a memory cell array including a first memory area and a second memory area, an input/output circuit including input/output lines for transmitting or receiving data bits and parity bits to or from the first and second memory areas, and an error correction circuit including a plurality of sub error correction circuits including a first sub error correction circuit for performing a first error correction operation on first data bits of the first memory area received through the input/output lines, and a second sub error correction circuit for performing a second error correction operation on second data bits of the second memory area received through the input/output lines. The first memory area has a higher bit error rate than the second memory area.

公开(公告)号：US20190362791A1

公开(公告)日：2019-11-28

申请号：US16533143

申请日：2019-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-woo KIM ,  Jae-kyu LEE ,  Ki-seok SUH ,  Hyeong-sun HONG ,  Yoo-sang HWANG ,  Gwan-hyeob KOH

IPC: G11C14/00 ,  H01L27/22 ,  H01L27/108 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L29/423 ,  H01L23/528 ,  H01L29/08 ,  H01L27/105 ,  H01L27/02 ,  G11C11/00 ,  G11C7/10

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.